GS2961A 3Gb/s, HD, SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing Key Features Applications Operation at 2.97Gb/s, 2.97/1.001Gb/s, 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s Application: Single Link (3G-SDI) Supports SMPTE 425M (Level A and Level B), SMPTE to Dual Link (HD-SDI) Converter 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI Integrated adaptive cable equalizer 10-bit HD-SDI GS2962 Link A Typical equalized length of Belden 1694A cable: HVF/PCLK 3G-SDI GS2961A 150m at 2.97Gb/s HVF/PCLK 10-bit HD-SDI GS2962 250m at 1.485Gb/s Link B 480m at 270Mb/s Integrated Reclocker with low phase noise, integrated VCO Application: Dual Link (HD-SDI) Serial digital reclocked, or non-reclocked output to Single Link (3G-SDI) Converter Ancillary data extraction HD-SDI 10-bit Link A HD-SDI 10-bit Deserializer FIFO Optional conversion from SMPTE 425M Level B to GS2961A HVF/PCLK 3G-SDI WR Level A for 1080p 50/60 4:2:2 10-bit HVF/PCLK GS2962 HD-SDI 10-bit Link B HD-SDI Parallel data bus selectable as either 20-bit or 10-bit 10-bit Deserializer FIFO HVF/PCLK GS2961A Comprehensive error detection and correction WR features Output H, V, F or CEA 861 Timing Signals GS4910 HVF 1.2V digital core power supply, 1.2V and 3.3V analog XTAL power supplies, and selectable 1.8V or 3.3V I/O power supply Description The GS2961A is a multi-rate SDI integrated Receiver which GSPI Host Interface includes complete SMPTE processing, as per SMPTE 425M, Wide temperature range of -40C to +85C 292M and SMPTE 259M-C. The SMPTE processing features Low power operation (typically 515mW) can be bypassed to support signals with other coding Small 11mm x 11mm 100-ball BGA package schemes. Pb-free and ROHS compliant The GS2961A integrates Gennum s adaptive cable equalizer technology, achieving unprecedented cable lengths and jitter tolerance. It features DC restoration to compensate for the DC content of SMPTE pathological signals. The device features an Integrated Reclocker with an internal VCO and a wide Input Jitter Tolerance (IJT) of 0.7UI. GS2961A 3Gb/s, HD, SD SDI Integrated Receiver 1 of 104 www.semtech.com Data Sheet 54385 - 2 September 2012 LOCKED H/HSync V/VSync F/De Rate det 1:0 Error Flags YANC/CANC A serial digital loop-through output is provided, which can Both SMPTE 425M Level A and Level B inputs are supported be configured to output either reclocked or non-reclocked with optional conversion from Level B to Level A for 1080p serial digital data. The serial digital output can be connected 50/59.94/60 4:2:2 10-bit inputs. to an external cable driver. In DVB-ASI mode, sync word detection, alignment and The device operates in one of four basic modes: SMPTE 8b/10b decoding is applied to the received data stream. mode, DVB-ASI mode, Data-Through mode or Standby In Data-Through mode all forms of SMPTE and DVB-ASI mode. processing are disabled, and the device can be used as a In SMPTE mode (the default operating mode), the GS2961A simple serial to parallel converter. performs full SMPTE processing, and features a number of The device can also operate in a lower power Standby data integrity checks and measurement capabilities. mode. In this mode, no signal processing is carried out and The device also supports ancillary data extraction, and can the parallel output is held static. provide entire ancillary data packets through Parallel data outputs are provided in 20-bit or 10-bit format host-accessible registers. It also provides a variety of other for 3Gb/s, HD and SD video rates, with a variety of mapping packet detection and error handling features. All of these options. As such, this parallel bus can interface directly with processing features are optional, and may be individually video processor ICs, and output data can be multiplexed enabled or disabled through register programming. onto 10 bits for a low pin count interface. Functional Block Diagram Crystal GSPI and Host Buffer/ JTAG Controller Interface Oscillator VBG LB CONT LF PCLK Illegal code Output Mux/ remap, Demux Flywheel TRS SMPTE 425M TRS/ ANC/ Reclocker Serial Mux DOUT 19:0 SDI Descramble, Video Detect Line Number/ Checksum Level B Level A with to Word Align, CRS EQ Buffer Standard Timing /352M Integrated Parallel Rate Detect 1080p 50/60 Insertion, Detect Extraction Extraction SDI VCO Converter 4:2:2 10-bit EDH Packet Insertion AGC+ AGC- DVB-ASI Decoder SDO Buffer Mux SDO I/O Control LOCKED GS2961A Functional Block Diagram GS2961A 3Gb/s, HD, SD SDI Integrated Receiver 2 of 104 Data Sheet 54385 - 2 September 2012 SDO EN/DIS VCO VDD VCO GND PLL VDD RC BYP PLL GND XTAL1 EQ VDD XTAL2 EQ GND XTAL OUT A VDD A GND BUFF VDD BUFF GND JTAG/HOST SDIN TDI SCLK TCLK CS TMS SDOUT TDO RESET TRST STANDBY IOPROC EN/DIS SMPTE BYPASS 20BIT/10BIT TIM861 SW EN DVB ASI CORE VDD CORE GND IO VDD IO GND