GS9092A
GenLINX III 270Mb/s Serializer for SDI and DVB-ASI
Key Features Description
SMPTE 259M-C compliant scrambling and NRZI to NRZ The GS9092A is a 270Mb/s serializer with an internal FIFO
encoding (with bypass) and an integrated cable driver. It contains all the necessary
blocks to realize a transmit solution for SD-SDI and
DVB-ASI sync word insertion and 8b/10b encoding
DVB-ASI applications.
Integrated Cable Driver
In addition to serializing the input data stream, the
Integrated line-based FIFO for data alignment/delay,
GS9092A performs NRZI-to-NRZ encoding and scrambling
clock phase interchange, DVB-ASI data packet
as per SMPTE 259M-C when operating in SMPTE mode.
insertion, and ancillary data packet insertion
When operating in DVB-ASI mode, the device will insert
User selectable additional processing features
K28.5 sync characters and 8b/10b encode the data prior to
including:
serialization.
ANC data checksum, and line number calculation
Parallel data inputs are provided for 10-bit multiplexed
and insertion
formats at SD signal rates. A 27MHz parallel clock input
TRS and EDH packet generation and insertion
signal is also required.
illegal code remapping
The integrated cable driver features an adjustable signal
Enhanced Gennum Serial Peripheral Interface (GSPI)
swing and common mode operating point offering fully
JTAG test interface
compliant SMPTE 259M-C cable driver connectivity.
+1.8V internal cable driver and core power supply
The GS9092A includes a range of data processing functions
Optional +1.8V or +3.3V digital I/O power supply
such as automatic standards detection and EDH support.
Small footprint (8mm x 8mm)
The device can also insert TRS signals, re-map illegal code
words, and generate and insert SMPTE 352M payload
Low power operation (typically 200mW)
identifier packets. All processing features are optional and
Pb-free and RoHS compliant
may be enabled/disabled via external control pin(s) and/or
host interface programming.
Applications
The GS9092A also incorporates a video line-based FIFO.
SMPTE 259M-C Serial Digital Interfaces
This FIFO may be used in four user-selectable modes to
DVB-ASI Serial Digital Interfaces
carry out tasks such as data delay, clock phase interchange,
MPEG packet insertion and clock rate interchange, and
ancillary data packet insertion.
The device may also be used as a low-latency
parallel-to-serial converter where the SMPTE scrambling
block will be the only processing feature enabled.
The GS9092A is Pb-free, and the encapsulation compound
does not contain halogenated flame retardant (RoHS
compliant).
GS9092A GenLINX III 270Mb/s Serializer for SDI and 1 of 61
www.semtech.com
DVB-ASI
Final Data Sheet
34715 - 5 February 2013dvb_asi
RESET
LF-
LF+
bypass
LB_CONT
RSV
PCLK
SDOUT_TDO
SDIN_TDI
SCLK_TCK
CS_TMS
JTAG_EN
STAT[2:0]
DETECT_TRS
DVB_ASI
IOPROC_EN
SMPTE_BYPASS
BLANK
WR_CLK
FIFO_EN
WR_RESET
GS9092A Functional Block Diagram
PLL
Programmable
I/O
SDO_EN
EDH
TRS Insertion
SDO
SMPTE
DVB-ASI Sync
Generation
Data Blank
352M
P --> S
Word Insert &
& SMPTE
Code Remap & Generation SDO
8b/10b Encode
Scramble
FIFO Flywheel
RSET
HOST Interface &
JTAG
Figure A: GS9092A Functional Block Diagram
GS9092A GenLINX III 270Mb/s Serializer for SDI and 2 of 61
DVB-ASI
Final Data Sheet
34715 - 5 February 2013