SX1231 WIRELESS & SENSING PRODUCTS DATASHEET SX1231 Transceiver Low Power Integrated UHF Transceiver VBAT1&2 VR ANA VR DIG RC Power Distribution System Oscillator / LNA Mixers Modulators Single to Differential RFIO RESET SPI RXTX RSSI AFC GND Division by 2, 4 or 6 DIO0 Tank PA0 DIO1 Inductor DIO2 Ramp & Loop Frac-N PLL VR PA Filter DIO3 Control Synthesizer DIO4 DIO5 XO PA BOOST 32 MHz PA1&2 XTAL GND GENERAL DESCRIPTION KEY PRODUCT FEATURES The SX1231 is a highly integrated RF transceiver capable of High Sensitivity: down to -120 dBm at 1.2 kbps operation over a wide frequency range, including the 433, High Selectivity: 16-tap FIR Channel Filter 868 and 915 MHz license-free ISM (Industry Scientific and Medical) frequency bands. Its highly integrated architecture Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm, 80 dB Blocking Immunity, no Image Frequency response allows for a minimum of external components whilst maintaining maximum design flexibility. All major RF Low current: Rx = 16 mA, 100nA register retention communication parameters are programmable and most of Programmable Pout: -18 to +17 dBm in 1dB steps them can be dynamically set. The SX1231 offers the unique advantage of programmable narrow-band and wide-band Constant RF performance over voltage range of chip communication modes without the need to modify external FSK Bit rates up to 300 kb/s components. The SX1231 is optimized for low power Fully integrated synthesizer with a resolution of 61 Hz consumption while offering high RF output power and channelized operation. TrueRF technology enables a low- FSK, GFSK, MSK, GMSK and OOK modulations cost external component count (elimination of the SAW Built-in Bit Synchronizer performing Clock Recovery filter) whilst still satisfying ETSI and FCC regulations. Incoming Sync Word Recognition APPLICATIONS 115 dB+ Dynamic Range RSSI Automatic RF Sense with ultra-fast AFC Automated Meter Reading Packet engine with CRC, AES-128 and 66-byte FIFO Wireless Sensor Networks Built-in temperature sensor and Low Battery indicator Home and Building Automation Wireless Alarm and Security Systems ORDERING INFORMATION Industrial Monitoring and Control Wireless M-BUS Part Number Package Delivery MOQ / Multiple SX1231IMLTRT QFN24 3000 pieces MARKETS Tape & Europe: EN 300-220-1 Reel SX1231ITSTRT TSSOP28 2500 pieces North America: FCC Part 15.247, 15.249, 15.231 Pb-free, Halogen free, RoHS/WEEE compliant product Narrow Korean and Japanese bands, Arib STD-T108 TSSOP: NiPdAu plated Rev. 7 - June 2013 Page 1 www.semtech.com Interpolation Decimation and & Filtering & Filtering Demodulator & Modulator Bit Synchronizer Packet Engine & 66 Bytes FIFO Control Registers - Shift Registers - SPI InterfaceSX1231 WIRELESS & SENSING PRODUCTS DATASHEET Table of contents Section Page 1. General Description ............................................................................................................................................... 10 1.1. Simplified Block Diagram ............................................................................................................................... 10 1.2. Pin and Marking Diagram ..............................................................................................................................11 1.3. Pin Description ...............................................................................................................................................12 2. Electrical Characteristics ....................................................................................................................................... 13 2.1. ESD Notice .................................................................................................................................................... 13 2.2. Absolute Maximum Ratings ........................................................................................................................... 13 2.3. Operating Range............................................................................................................................................ 13 2.4. Chip Specification ..........................................................................................................................................14 2.4.1. Power Consumption.................................................................................................................................. 14 2.4.2. Frequency Synthesis................................................................................................................................. 14 2.4.3. Receiver .................................................................................................................................................... 15 2.4.4. Transmitter ................................................................................................................................................ 16 2.4.5. Digital Specification ...................................................................................................................................17 3. Chip Description .................................................................................................................................................... 18 3.1. Power Supply Strategy .................................................................................................................................. 18 3.2. Low Battery Detector ..................................................................................................................................... 18 3.3. Frequency Synthesis ..................................................................................................................................... 18 3.3.1. Reference Oscillator.................................................................................................................................. 18 3.3.2. CLKOUT Output ........................................................................................................................................19 3.3.3. PLL Architecture........................................................................................................................................ 19 3.3.4. Lock Time ..................................................................................................................................................20 3.3.5. Lock Detect Indicator................................................................................................................................. 20 3.4. Transmitter Description ..................................................................................................................................21 3.4.1. Architecture Description ............................................................................................................................ 21 3.4.2. Bit Rate Setting ......................................................................................................................................... 21 3.4.3. FSK Modulation......................................................................................................................................... 22 3.4.4. OOK Modulation........................................................................................................................................ 23 3.4.5. Modulation Shaping................................................................................................................................... 23 3.4.6. Power Amplifiers ....................................................................................................................................... 23 3.4.7. Over Current Protection ............................................................................................................................ 24 3.5. Receiver Description ......................................................................................................................................25 3.5.1. Block Diagram........................................................................................................................................... 25 3.5.2. LNA - Single to Differential Buffer ............................................................................................................. 25 3.5.3. Automatic Gain Control ............................................................................................................................. 26 3.5.4. Continuous-Time DAGC............................................................................................................................ 27 3.5.5. Quadrature Mixer - ADCs - Decimators ....................................................................................................28 3.5.6. Channel Filter............................................................................................................................................ 28 3.5.7. DC Cancellation ........................................................................................................................................ 29 Rev. 7 - June 2013 Page 2 www.semtech.com