XE1203FI063TRLF Semtech

XE1203F XE1203F 433 MHz / 868 MHz / 915 MHz Low-Power, Integrated UHF Transceiver GENERAL DESCRIPTION KEY PRODUCT FEATURES The XE1203F is a single chip transceiver operating RF output power: up to +15 dBm in the 433, 868 and 915 MHz license-free ISM High reception sensitivity: down to 114 dBm (Industry Scientific and Medical) frequency bands. Its (typical) highly integrated architecture allows for minimum Low power consumption: external components while maintaining design R = 14 mA T = 62 mA 15 dBm (typical) X X flexibility. All major RF communication parameters Supply voltage down to 2.4V are programmable and most of them can be Data rate from 1.2 to 152.3 kbit/s, NRZ coding dynamically set. The XE1203F offers the excellent Konnex-compatible operation mode advantage of high data rate communication at rates 11-bit Barker encoder/decoder of up to 152.3 kbit/s, without the need to modify the On-chip frequency synthesizer with minimum number or parameters of the external components. frequency resolution of 500 Hz The XE1203F is optimized for low power Continuous phase 2-level FSK modulation consumption while offering high RF output power and Received data pattern recognition exceptional receiver sensitivity. The device is suitable Bit-Synchronizer for incoming data/clock for applications which have to satisfy either the synchronization and recovery European (ETSI-300-220) or the North American (FCC part 15) regulatory standards. TrueRF RSSI (Received Signal Strength Indicator) technology enables a low cost external component FEI (Frequency Error Indicator) count (elimination of the SAW filter) whilst still RoHS green package satisfying ETSI and FCC regulations. APPLICATIONS ORDERING INFORMATION Automated Meter Reading (AMR) Part number Temperature Package Home Automation and Access Control range High-Quality Speech, Music and Data over RF XE1203FI063TRLF -40 C to +85 C MLPQ48 Applications requiring Konnex-compatibility Rev 2 December 2008 www.semtech.com 1 XE1203F Table of Contents 1 Functional Block Diagram.................................................................................................................. 3 2 Pin description .................................................................................................................................... 4 3 Electrical Characteristics................................................................................................................... 5 3.1 Absolute Maximum Operating Ranges................................................................................................. 5 3.2 Specifications........................................................................................................................................ 5 3.2.1 Operating Range................................................................................................................................... 5 3.2.2 Electrical Specifications ........................................................................................................................ 5 4 GENERAL DESCRIPTION................................................................................................................... 7 4.1 The Receiver Section............................................................................................................................ 7 4.1.1 LNA & Receiver modes......................................................................................................................... 8 4.1.2 Demodulation chain .............................................................................................................................. 8 4.1.3 Demodulator.......................................................................................................................................... 8 4.1.4 Bit synchronizer .................................................................................................................................... 9 4.1.5 The DATA and DATAIN pins .............................................................................................................. 10 4.1.6 Pattern recognition block .................................................................................................................... 10 4.1.7 RSSI.................................................................................................................................................... 10 4.1.8 Frequency Error Indicator FEI ......................................................................................................... 12 4.2 The Transmitter Section...................................................................................................................... 13 4.2.1 Transmitter.......................................................................................................................................... 13 4.2.2 Barker encoder/decoder ..................................................................................................................... 15 4.3 The Frequency Synthesizer................................................................................................................ 16 4.3.1 Clock Output for external processor ................................................................................................... 17 5 SERIAL Interface definition AND Principles of operation ............................................................ 18 5.1 Serial Control Interface ....................................................................................................................... 18 5.2 Configuration and Status registers ..................................................................................................... 20 5.2.1 The ConfigSwitch Register ................................................................................................................. 20 5.2.2 RTParam Configuration Register........................................................................................................ 22 5.2.3 FSParam Configuration Register........................................................................................................ 23 5.2.4 SWParam Configuration Register - switching parameters ................................................................. 24 5.2.5 DataOut Status Register..................................................................................................................... 25 5.2.6 ADParam Configuration Register ....................................................................................................... 25 5.2.7 Pattern register ................................................................................................................................... 27 5.2.8 Test Registers and additional settings................................................................................................ 28 5.3 Operating Modes ................................................................................................................................28 5.3.1 Standard power up sequence for the receiver and transmitter .......................................................... 28 5.4 Selection of the reference frequency.................................................................................................. 29 5.5 Clock Output Interface ........................................................................................................................ 30 5.6 Default settings at power-up ............................................................................................................... 30 6 Application Information.................................................................................................................... 31 6.1 RECEIVER Matching network ............................................................................................................ 31 6.2 Transmitter matching network ............................................................................................................ 31 6.3 VCO tank............................................................................................................................................. 34 6.4 Loop filter of the frequency synthesizer.............................................................................................. 34 6.5 frequency synthesizer Reference crystal............................................................................................ 35 7 Revision History................................................................................................................................36 8 Packaging information ..................................................................................................................... 37 Semtech 2008 www.semtech.com 2