SLG7NT4100V Silego

SLG7NT4100 SLG7NT4100 VR Enable and Discharge General Description Pin Configuration Silego SLG7NT4100 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm VDD 1 12 VR2 DISCH TDFN package which is optimal for using with small VR1 EN1 IN 2 11 VR2 EN OUT devices. VR1 EN2 IN 3 10 VR2 EN3 IN VR1 EN3 IN 4 9 VR2 EN2 IN VR1 EN OUT 5 8 VR2 EN1 IN Features VR1 DISCH Low Power Consumption 6 7 GND 3.3V Supply Voltage Thermal Pad RoHS Compliant / Halogen-Free TDFN-12 connected to GND TOP VIEW Pb-Free TDFN-12 Package Output Summary 2 Outputs Open Drain 2X current 2 Outputs Push Pull Silego Technology, Inc. Rev 1.01 SLG7NT4100 DB r101 Revised December 11, 2012 SLG7NT4100 GP r002 SLG7NT4100 VR Enable and Discharge Block Diagram Typical Application Circuit +3.3V C1 100nF U1 1 12 VR2 DISCH OUT VDD data I/O VR1 EN1 IN 2 11 VR2 EN OUT IN OUT data I data I/O VR1 EN2 IN 3 10 IN data I/O data I/O 4 9 VR1 EN3 IN IN data I/O data I/O 5 8 data I/O data I/O 6 7 data I/O GND SLG7NT4100 VR1 DISCH OUT VR2 EN1 IN IN VR1 EN OUT OUT VR2 EN2 IN IN VR2 EN3 IN IN SLG7NT4100 DB r101 Page 2