AN685 LAYOUT DESIGN GUIDE FOR THE Si4455/435X RF ICS 1. Introduction This application note provides guidelines and design examples to help users design PCBs for the next generation EZRadio RF ICs, such as the Si4455/435x devices, using good design practices that allow for high quality RF performance. The RF performance and the critical maximum peak voltage on the output pin strongly depends on the PCB layout as well as the design of the matching networks. The matching principles are described in detail in AN693: Si4455 Low Power PA Matching. Furthermore, these types of RF ICs are also applicable in the RF Stick and RF pico board solutions where a PCB antenna is used, which also requires some considerations in the layout design. For optimal performance, Silicon Labs recommends using the PCB layout design suggestions described in the following sections. 2. Design Recommendations when Using Si4455/435x RF ICs Extensive testing has been completed using reference designs provided by Silicon Labs. It is recommended that designers use the reference designs as-is since they minimize de-tuning effects caused by parasitics and generated by component placement and PCB routing. When layouts as shown by the reference designs cannot be followed (as a result of PCB size and shape limitations), then the following layout design rules are recommended. The Si4455 transceiver RF chip uses Class-E TX matching network and a 4-element matching balun on the RX side in Direct Tie configuration (where the TX and RX paths are connected together directly without any additional RF switch). Meanwhile, the Si435x receiver RF chip uses only the 4-element matching balun. Rev. 0.4 Copyright 2014 by Silicon Laboratories AN685AN685 3. Guidelines for Layout Design when Using the Si4455 RF IC Examples shown in this section are based upon the layout of the 4355-PRXB434M (4355CPRXB434M) pico board. The schematic of the RF part of the Class-E Direct Tie type matching network for the Si4455 chip is shown in Figure 1. This Class-E type of matching provides very good efficiency with a low current consumption, and the typical output power is +10 dBm. The matching component values should be chosen based on the operating frequency. During TX mode operation, the built-in LNA protection circuit turns on (refer to application note, AN693: Si4455 Low Power PA Matching for more details). In this case, the dc path from the output of the matching network to the GND is not blocked through the RX side, therefore, a dc blocking capacitor (CC1) is necessary. For the Direct Tie type matching, the coupling between the RX and TX sides is not critical since no harmonic leakage through the coupled RX path occurs as both of them are filtered after the common connection point. Beside the TX output, unwanted harmonics appear on other pins due to coupling inside the chip. Depending on the actual output power level and the relevant EMC regulation, these emissions can cause problems if they are radiated by the traces of a custom board with poor RF design. Similarly, in RX mode the leakage of the VCO reference signal appears. That is why Silicon Labs reference design pico boards incorporate additional filtering on the GPIO 2, GPIO 3, and SDN traces. Figure 1. Schematic of the RF Part of the Class-E Direct Tie Type Matching Network for the Si4455 Chip 2 Rev. 0.4