Si500D
DIFFERENTIAL OUTPUT SILICON OSCILLATOR
Features
Quartz-free, MEMS-free, and PLL-free all-silicon Footprint compatible with industry-
oscillator standard 3.2 x 5.0 mm XOs
Any output frequencies from 0.9 to 200 MHz CMOS, SSTL, LVPECL, LVDS, and HCSL
versions available
Short lead times
Driver stopped, tri-state, or powerdown
Excellent temperature stability (20 ppm)
operation
Highly reliable startup and operation
RoHS compliant
High immunity to shock and vibration
1.8, 2.5, or 3.3 V options
Low jitter: <1.5 ps rms
Low power
0 to 85 C operation includes 10-year aging in hot
More than 10x better fit rate than
environments
competing crystal solutions
Specifications
Parameters Condition Min Typ Max Units
Frequency Range 0.9 200 MHz
Temperature stability,
10 ppm
0 to +70 C
Temperature stability,
20 ppm
0 to +85 C
Frequency Stability
Total stability,
150 ppm
1
0 to +70 C operation
Total stability,
250 ppm
2
0 to +85 C operation
Commercial 0 70 C
Operating Temperature
Extended commercial 0 85 C
Storage Temperature 55 +125 C
1.8 V option 1.71 1.98 V
Supply Voltage 2.5 V option 2.25 2.75 V
3.3 V option 2.97 3.63 V
Notes:
1. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 C, shock, vibration, and one solder reflow.
2. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 C, shock, vibration, and one solder reflow.
3. See AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators for further details regarding
output clock termination recommendations.
4. V = .5 x V .
TT DD
5. V = .45 x V .
TT DD
Rev. 1.1 10/11 Copyright 2011 by Silicon Laboratories Si500DSi500D
Parameters Condition Min Typ Max Units
LVPECL 34.0 36.0 mA
Low Power LVPECL 19.3 22.2 mA
LVDS 14.9 16.5 mA
HCSL 25.3 29.3 mA
Differential CMOS(3.3 V option,
33 36 mA
10 pF on each output, 200 MHz)
Supply Current Differential CMOS(3.3 V option,
16 mA
1 pFon each output, 40 MHz)
Differential SSTL-3.3 24.5 27.7 mA
Differential SSTL-2.5 24.3 26.7 mA
Differential SSTL-1.8 22.2 25 mA
Tri-State 9.7 10.7 mA
Powerdown 1.0 1.9 mA
Output Symmetry V = 0 46 13 ns/T 54 + 13 ns/T %
DIFF CLK CLK
LVPECL/LVDS 460 ps
3
Rise and Fall Times (20/80%) HCSL/Differential SSTL 800 ps
Differential CMOS, 15 pF, >80 MHz 1.1 1.6 ns
Mid-level V 1.5 V 1.34 V
LVPECL Output Option
DD DD
3
(DC coupling, 50 to V 2.0 V)
Diff swing .720 .880 V
DD
PK
Low Power LVPECL Output Option Mid-level N/A V
(AC coupling, 100 Differential
Diff swing .68 .95 V
3
PK
Load)
Mid-level 1.15 1.26 V
LVDS Output Option (2.5/3.3 V)
3
(R = 100 diff)
Diff swing 0.25 0.45 V
TERM
PK
Mid-level 0.85 0.96 V
LVDS Output Option (1.8 V)
3
(R = 100 diff)
Diff swing 0.25 0.45 V
TERM
PK
Mid-level 0.35 0.425 V
3
HCSL Output Option Diff swing 0.65 0.82 V
PK
DC termination per pad 45 55
V , sourcing 9 mA V 0.6 V
OH DD
3
CMOS Output Voltage
V , sinking 9 mA 0.6 V
OL
V V + 0.375
OH TT
4
SSTL-1.8 Output Voltage V
V V 0.375
OL TT
V V + 0.48
OH TT
4
SSTL-2.5 Output Voltage V
V V 0.48
OL TT
V V + 0.48
OH TT
5
SSTL-3.3 Output Voltage V
V V 0.48
OL TT
From time V crosses min spec
DD
Powerup Time 2 ms
supply
OE Deassertion to Clk Stop 250 + 3 x T ns
CLK
Return from Output Driver Stopped
250 + 3 x T ns
CLK
Mode
Return From Tri-State Time 12 + 3 x T s
CLK
Notes:
1. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
first-year aging at 25 C, shock, vibration, and one solder reflow.
2. Inclusive of 25 C initial frequency accuracy, operating temperature range, supply voltage change, output load change,
ten-year aging at 85 C, shock, vibration, and one solder reflow.
3. See AN409: Output Termination Options for the Si500S and Si500D Silicon Oscillators for further details regarding
output clock termination recommendations.
= .5 x V .
4. V
TT DD
5. V = .45 x V .
TT DD
2 Rev. 1.1