Si512/513 DUAL FREQUENCY CRYSTAL OSCILLATOR (XO) 100 kHZ TO 250 MHZ Features Supports any frequency from 3.3, 2.5, or 1.8 V operation Si5602 100 kHz to 250 MHz Differential (LVPECL, LVDS, Two selectable output frequencies HCSL) or CMOS output options Low-jitter operation Optional integrated 1:2 CMOS fanout buffer 2 to 4 week lead times Runt suppression on OE and Total stability includes 10-year power on aging 2.5x3.2mm Industry standard 5x7, 3.2x5, and Comprehensive production test 2.5x3.2 mm packages coverage includes crystal ESR and DLD Pb-free, RoHS compliant 5x7mm and 3.2x5mm o On-chip LDO regulator for power 40 to 85 C operation supply noise filtering Ordering Information: Applications See page 13. SONET/SDH/OTN Broadcast video Gigabit Ethernet Switches/routers Pin Assignments: Fibre Channel/SAS/SATA Telecom See page 12. PCI Express FPGA/ASIC clock generation Description FS 1 6 VDD The Si512/513 dual frequency XO utilizes Silicon Laboratories advanced OE 2 5 NC PLL technology to provide any frequency from 100 kHz to 250 MHz. Unlike a traditional XO where a different crystal is required for each output frequency, GND 3 4 CLK the Si512/513 uses one fixed crystal and Silicon Labs proprietary any- Si512 CMOS Dual XO frequency synthesizer to generate any frequency across this range. This IC- based approach allows the crystal resonator to provide enhanced reliability, OE 1 6 VDD improved mechanical robustness, and excellent stability. In addition, this FS 2 5 solution provides superior supply noise rejection, simplifying low jitter clock NC generation in noisy environments. The Si512/513 is factory-configurable for a GND 3 4 CLK wide variety of user specifications, including frequency, supply voltage, output format, output enable polarity, and stability. Specific configurations are Si513 CMOS Dual XO factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency 1 6 V FS DD oscillators. OE 2 5 CLK GND 3 4 CLK+ Functional Block Diagram Si512 LVDS/LVPECL/HCSL/CMOS V DD Dual XO 1 6 VDD Power Supply Filtering OE OE FS 2 5 CLK Fixed Any-Frequency CLK+ Frequency 0.1 to 250 MHz GND 3 4 CLK+ Oscillator DSPLL Synthesis CLK Si513 LVDS/LVPECL/HCSL/CMOS Dual XO GND FS Rev. 1.2 6/18 Copyright 2018 by Silicon Laboratories Si512/13Si512/513 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages 10 3. Pin Descriptions .11 3.1. Dual CMOS Buffer 12 4. Ordering Information .13 5. Package Outline Diagram, 5 x 7 mm, 6-pin .14 6. PCB Land Pattern: 5 x 7 mm, 6-pin 15 7. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin 16 8. PCB Land Pattern: 3.2 x 5.0 mm 17 9. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin 18 10. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin 20 11. Top Marking .21 11.1. Si512/513 Top Marking 21 11.2. Top Marking Explanation 21 Document Change List .22 2 Rev. 1.2