514BBB001011BAG Silicon Labs

Si514 2 ANY-FREQUENCY I C PROGRAMMABLE XO (100 kHZ TO 250 MHZ) Features Si5602 Programmable to any frequency On-chip LDO for power supply from 100 kHz to 250 MHz noise filtering 0.026 ppb frequency tuning 3.3, 2.5, or 1.8 V operation resolution Differential (LVPECL, LVDS, Glitch suppression on OE, power HCSL) or CMOS output options on and frequency transitions Optional integrated 1:2 CMOS 5x7mm, 3.2x5mm 2.5x3.2mm Low jitter operation fanout buffer 2- to 4-week lead times Industry standard 5x7, 3.2x5, and 2.5x3.2 mm packages Total stability includes 10-year Ordering Information: o aging 40 to 85 C operation See page 28. Comprehensive production test coverage includes crystal ESR and DLD Pin Assignments: Applications See page 27. All-digital PLLs Datacom DAC+ VCXO replacement Industrial automation 1 6 V SDA DD SONET/SDH/OTN FPGA/ASIC clock generation 3G-SDI/HD-SDI/SDI FPGA synchronization SCL 2 5 CLK Description 2 GND 3 4 CLK+ The Si514 user-programmable I C XO utilizes Silicon Laboratories advanced PLL technology to provide any frequency from 100 kHz to 250 MHz with programming resolution of 0.026 parts per billion. The Si514 uses a single integrated crystal and Silicon Labs proprietary DSPLL synthesizer to generate any frequency across this 2 range using simple I C commands. Ultra-fine tuning resolution replaces DACs and VCXOs with an all-digital PLL solution that improves performance where synchronization is necessary or in free-running reference clock applications. This solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. Crystal ESR and DLD are individually production-tested to guarantee performance and enhance reliability. The Si514 is factory-configurable for a wide variety of user specifications, including 2 startup frequency, I C address, supply voltage, output format, and stability. Specific configurations are factory-programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. Functional Block Diagram Rev. 1.2 6/18 Copyright 2018 by Silicon Laboratories Si514Si514 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Solder Reflow and Rework Requirements for 2.5x3.2 mm Packages 11 3. Functional Description .12 3.1. Programming a New Output Frequency 12 3.2. Programming a Small Frequency Change (sub 1000 ppm) 13 3.3. Programming a Large Frequency Change (> 1000 ppm) 14 4. All-Digital PLL Applications .18 5. User Interface .19 5.1. Register Map .19 5.2. Register Detailed Description 20 5.3. I2C Interface .25 6. Pin Descriptions .27 6.1. Dual CMOS (1:2 Fanout Buffer) 27 7. Ordering Information .28 8. Package Outline Diagram: 5 x 7 mm, 6-pin .29 9. PCB Land Pattern: 5 x 7 mm, 6-pin 30 10. Package Outline Diagram: 3.2 x 5.0 mm, 6-pin .31 11. PCB Land Pattern: 3.2 x 5.0 mm, 6-pin 32 12. Package Outline Diagram: 2.5 x 3.2 mm, 6-pin .33 13. PCB Land Pattern: 2.5 x 3.2 mm, 6-pin 35 14. Top Marking .36 14.1. Si514 Top Marking .36 14.2. Top Marking Explanation 36 Document Change List .37 2 Rev. 1.2