530AC000338DG Silicon Labs

Si530/531 REVISION D CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ) Features Si5602 Available with any-rate output Internal fixed crystal frequency frequencies from 10 MHz to 945 MHz ensures high reliability and low and select frequencies to 1.4 GHz aging Available CMOS, LVPECL, 3rd generation DSPLL with superior LVDS, and CML outputs jitter performance 3.3, 2.5, and 1.8 V supply options 3x better frequency stability than Industry-standard 5 x 7 mm SAW-based oscillators package and pinout Pb-free/RoHS-compliant Ordering Information: Applications See page 7. SONET/SDH Test and measurement Networking Clock and data recovery Pin Assignments: SD/HD video FPGA/ASIC clock generation See page 6. Description (Top View) The Si530/531 XO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low jitter clock at high frequencies. The Si530/531 is available 1 6 V NC DD with any-rate output frequency from 10 to 945 MHz and select frequencies to 1400 MHz. Unlike a traditional XO, where a different crystal is required for OE 2 5 CLK each output frequency, the Si530/531 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, GND 3 4 CLK+ DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in Si530 (LVDS/LVPECL/CML) communication systems. The Si530/531 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, and temperature stability. Specific configurations are factory V 1 6 DD OE programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. NC 2 5 NC Functional Block Diagram GND 3 4 CLK V CLK CLK+ DD Si530 (CMOS) V 1 6 DD OE Any-rate Fixed 101400 MHz Frequency DSPLL NC 2 5 CLK XO Clock Synthesis GND 3 4 CLK+ Si531 (LVDS/LVPECL/CML) OE GND Rev. 1.5 6/18 Copyright 2018 by Silicon Laboratories Si530/531Si530/531 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit 1 V 3.3 V option 2.97 3.3 3.63 V Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Supply Current I Output enabled DD LVPECL 121 111 CML 99 108 mA 90 LVDS 98 81 CMOS 88 Tristate mode 60 75 mA 2 Output Enable (OE) V 0.75 x V V IH DD V 0.5 V IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See Section 3.Ordering Informatio on page 7 for further details. 2. OE pin includes a 17 k pullup resistor to V . DD Table 2. CLK Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Unit 1,2 f LVPECL/LVDS/CML 10 945 MHz Nominal Frequency O CMOS 10 160 MHz Initial Accuracy Measured at +25 C at time of f 1.5 ppm i shipping 1,3 Temperature Stability 7 +7 20 +20 ppm 50 +50 Aging Frequency drift over first year 3 ppm f a Frequency drift over 20 year 10 ppm life Notes: 1. See Section 3.Ordering Informatio on page 7 for further details. 2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz. 3. Selectable parameter specified by part number. 4. Time from powerup or tristate mode to f . O 2 Rev. 1.5