Ultra Series Crystal Oscillator
Si544 Data Sheet
Ultra Low Jitter I2C Programmable XO (150 fs), 0.2 to 1500 MHz
th
The Si544 Ultra Series oscillator utilizes Silicon Laboratories advanced 4
KEY FEATURES
generation DSPLL technology to provide an ultra-low jitter, low phase noise
clock at any output frequency. The device is user-programmed via simple
I2C programmable to any frequency from 0.2 to
I2C commands to provide any frequency from 0.2 to 1500 MHz with <1 ppb
1500 MHz with < 1 ppb resolution
resolution and maintains exceptionally low jitter for both integer and fraction-
Very low jitter: 150 fs Typ RMS (12 kHz 20 MHz)
al frequencies across its operating range. The Si544 offers excellent reliabili-
ty and frequency stability as well as guaranteed aging performance. On-chip Configure up to 4 pin-selectable startup frequencies
power supply filtering provides industry-leading power supply noise rejection,
I2C interface supports 100 kbps, 400 kbps, and 1
simplifying the task of generating low jitter clocks in noisy systems that use
Mbps (Fast Mode Plus)
switched-mode power supplies. The Si544 has a dramatically simplified sup-
Excellent PSNR and supply noise immunity: 80
ply chain that enables Silicon Labs to ship custom frequency samples 1-2
dBc Typ
weeks after receipt of order. Unlike a traditional XO, where a different crystal
3.3 V, 2.5 V and 1.8 V V supply operation from
DD
is required for each output frequency, the Si544 uses one simple crystal and
the same part number
a DSPLL IC-based approach to provide the desired output frequency. The
LVPECL, LVDS, CML, HCSL, CMOS, and Dual
Si544 is factory-configurable for a wide variety of user specifications, includ-
CMOS output options
ing startup frequency, I2C address, output format, and OE pin location/
2.5x3.2, 3.2x5, 5x7 mm package footprints
polarity. Specific configurations are factory-programmed at time of shipment,
Samples available with 1-2 week lead times
eliminating the long lead times associated with custom oscillators.
APPLICATIONS
Pin Assignments
SDA
100G/200G/400G OTN, coherent optics, PAM4
7
OE/FS/NC 1 6 VDD
10G/40G/100G optical ethernet
3G-SDI/12G-SDI/24G-SDI broadcast video
NC/OE/FS 2 5 CLK
Servers, switches, storage, search acceleration
GND 3 4 CLK+
8 Test and measurement
FPGA/ASIC clocking
SCL
(Top View)
Fixed Frequency
Frequency Flexible
Pin # Descriptions
Low
Crystal DSPLL
Noise
Driver
DCO
1, 2 Selectable via ordering option
Digital Digital
OSC Phase Error
Phase Loop
OE = Output enable; FS = Frequency Select; NC = No connect
Cancellation
Detector Filter
Flexible
Phase Error
Formats,
3 GND = Ground 1.8V 3.3V
Fractional
Operation
Divider
NVM
4 CLK+ = Clock output
Control Power Supply Regulation
5 CLK- = Complementary clock output. Not used for CMOS.
OE, Frequency Select Built-in Power Supply
(I2C and Pin Control) Noise Rejection
6 VDD = Power supply
7 SDA = I2C Serial Data
8 SCL = I2C Serial Clock
silabs.com | Building a more connected world. Rev. 1.1 Si544 Data Sheet
Ordering Guide
1. Ordering Guide
The Si544 XO supports a variety of options including startup frequency, output format, and OE pin location/polarity, as shown in the
chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks.
Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to
access this tool and for further ordering instructions.
2
XO Series Description Temp Stability Total Stability Package Temperature Grade
544 I2C Oscillator A 20 ppm 50 ppm A 5x7 mm G -40 to 85 C
B 10 ppm 25 ppm B 3.2x5 mm
C 7 ppm 20 ppm C 2.5x3.2 mm
544 A A A A - - - - - - A B G R
Device Revision
Order
Code
Supported Frequency Range Code Reel
Signal Format VDD Range
Option
A 0.2-1500 MHz
R Tape and Reel
LVPECL 2.5, 3.3 V A
B 0.2-800 MHz
<Blank> Coil Tape
LVDS 1.8, 2.5, 3.3 V B
C 0.2-325 MHz (CMOS available to 250 MHz)
CMOS 1.8, 2.5, 3.3 V C
CML 1.8, 2.5, 3.3 V D
Frequency
Pinout Option
Description
HCSL 1.8, 2.5, 3.3 V E
3
Code
FS0 FS1
Code OE Pin OE Polarity
Dual CMOS
(Dual) (Quad)
1.8, 2.5, 3.3 V F
(In-Phase)
The Si544 supports one, two, or
-- --
A Pin 1 Active High
Dual CMOS
four user-defined startup
1.8, 2.5, 3.3 V G B Pin 1 Active Low -- --
(Complementary)
frequencies in the range
C Pin 2 Active High -- --
1
Custom 1.8, 2.5, 3.3 V X selected by the Supported
D Pin 2 Active Low -- --
Frequency Range code. A user-
xxxxxx
defined 7-bit I2C address is
E Pin 1 Active High Pin 2 --
supported. Each unique startup
F Pin 1 Active Low Pin 2 --
configuration and I2C address
G Pin 2 Active High Pin 1 --
combination is assigned a 6-digit
H Pin 2 Active Low Pin 1 --
code.
J -- -- Pin 1 Pin 2
Single Dual Quad
Codes A, B Codes E, F Code J
SDA SDA SDA
7 7 7
OE 1 6 VDD OE 1 6 VDD FS0 1 6 VDD
NC 2 5 CLK FS0 2 5 CLK FS1 2 5 CLK
GND 3 4 CLK+ GND 3 4 CLK+ GND 3 4 CLK+
8 8 8
SCL SCL SCL
Codes C, D Codes G, H
SDA SDA
7 7
NC 1 6 VDD FS0 1 6 VDD
OE 2 5 CLK OE 2 5 CLK
GND 3 4 CLK+ GND 3 4 CLK+
8 8
SCL SCL
If replacing Si570A-K, use Code C
If replacing Si570M-W, use Code D
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 C.
3. Create custom part numbers at www.silabs.com/oscillators.
silabs.com | Building a more connected world. Rev. 1.1 | 2