Ultra Series Crystal Oscillator
Si546 Data Sheet
Ultra Low Jitter Dual Any-Frequency XO (80 fs), 0.2 to 1500
KEY FEATURES
MHz
Available with any two selectable frequencies
th
The Si546 Ultra Series oscillator utilizes Silicon Laboratories advanced 4 gen-
from 200 kHz to 1500 MHz
eration DSPLL technology to provide an ultra-low jitter, low phase noise clock at
Ultra low jitter: 80 fs Typ RMS
two selectable frequencies. The device is factory-programmed to provide any two
(12 kHz 20 MHz)
selectable frequencies from 0.2 to 1500 MHz with <1 ppb resolution and maintains
Excellent PSRR and supply noise immunity:
exceptionally low jitter for both integer and fractional frequencies across its operat-
80 dBc Typ
ing range. The Si546 offers excellent reliability and frequency stability as well as
7 ppm stability option (40 to 85 C)
guaranteed aging performance. On-chip power supply filtering provides industry-
3.3 V, 2.5 V and 1.8 V V supply operation
DD
leading power supply noise rejection, simplifying the task of generating low jitter
from the same part number
clocks in noisy systems that use switched-mode power supplies. Offered in indus-
LVPECL, LVDS, CML, HCSL, CMOS, and
try-standard 3.2x5 mm and 5x7 mm footprints, the Si546 has a dramatically simpli-
Dual CMOS output options
fied supply chain that enables Silicon Labs to ship custom frequency samples 1-2
3.25, 5x7 mm package footprints
weeks after receipt of order. Unlike a traditional XO, where a different crystal is re-
quired for each output frequency, the Si546 uses one simple crystal and a DSPLL
Samples available with 1-2 week lead times
IC-based approach to provide the desired output frequencies. This process also
guarantees 100% electrical testing of every device. The Si546 is factory-configura-
APPLICATIONS
ble for a wide variety of user specifications, including frequency, output format,
and OE pin location/polarity. Specific configurations are factory-programmed at
100G/200G/400G OTN, coherent optics
time of shipment, eliminating the long lead times associated with custom oscilla-
10G/25G/40G/100G Ethernet
tors.
3G-SDI/12G-SDI/24G-SDI broadcast video
Pin Assignments
Servers, switches, storage, NICs, search
acceleration
Test and measurement
OE/FS 1 6 VDD
Clock and data recovery
FPGA/ASIC clocking
FS/OE 2 5 CLK-
3 4 CLK+
GND
(Top View)
Fixed Frequency
Pin # Descriptions Frequency Flexible
Low
Crystal DSPLL
Noise
Driver
1, 2 Selectable via ordering option
DCO
OE = Output enable; FS = Frequency Select Digital Digital
OSC
Phase Error
Phase Loop
Cancellation
Detector Filter
Flexible
3 GND = Ground
Phase Error
Formats,
1.8V 3.3V
Fractional
Operation
4 CLK+ = Clock output
Divider
NVM
5 CLK- = Complementary clock output. Not used for CMOS.
Control Power Supply Regulation
6 VDD = Power supply
OE, Frequency Select Built-in Power Supply
(Pin Control) Noise Rejection
silabs.com | Building a more connected world. Rev. 1.0 Si546 Data Sheet
Ordering Guide
1. Ordering Guide
The Si546 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart
below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Silicon
Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access
this tool and for further ordering instructions.
2
XO Series Description Temp Stability Total Stability Package Temperature Grade
546 Dual Frequency A 5x7 mm G -40 to 85 C
A 20 ppm 50 ppm
B 3.2x5 mm
B 10 ppm 25 ppm
C
7 ppm 20 ppm
546 A A A - - - - - - A B G R
Device Revision
OE FS
Order
OE Polarity
Signal Format VDD Range
Pin Pin
Option
A Pin 1 Active High Pin 2
Reel
LVPECL 2.5, 3.3 V A
B Pin 1 Active Low Pin 2
R Tape and Reel
LVDS 1.8, 2.5, 3.3 V B
C Pin 2 Active High Pin 1
<Blank> Coil Tape
CMOS 1.8, 2.5, 3.3 V C
D Pin 2 Active Low Pin 1
CML 1.8, 2.5, 3.3 V D
3
HCSL 1.8, 2.5, 3.3 V E
Frequency Code Description
Dual CMOS
1.8, 2.5, 3.3 V F
(In-Phase) Two unique frequencies can be specified
within the supported range of the selected
Dual CMOS
1.8, 2.5, 3.3 V G
signal format. Either frequency can be
(Complementary)
xxxxxx
assigned to FS=0 or FS=1. A six digit numeric
1
Custom 1.8, 2.5, 3.3 V X
code will be assigned for the specific
combination of frequencies.
Notes:
1. Contact Silicon Labs for non-standard configurations.
2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 20 year aging at 70 C.
3. Create custom part numbers at www.silabs.com/oscillators.
1.1 Technical Support
Frequently Asked Questions (FAQ) www.silabs.com/Si546-FAQ
Oscillator Phase Noise Lookup Utility www.silabs.com/oscillator-phase-noise-lookup
Quality and Reliability www.silabs.com/quality
Development Kits www.silabs.com/oscillator-tools
silabs.com | Building a more connected world. Rev. 1.0 | 2