Si552 REVISION D DUAL FREQUENCY VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ Features Available with any-rate output Internal fixed crystal frequency frequencies from 10945 MHz and ensures high reliability and low Si5602 selected frequencies to 1.4 GHz aging Two selectable output frequencies Available CMOS, LVPECL, LVDS, and CML outputs 3rd generation DSPLL with superior 3.3, 2.5, and 1.8 V supply options jitter performance Industry-standard 5 x 7 mm 3x better frequency stability than package and pinout SAW-based oscillators Pb-free/RoHS-compliant Applications Ordering Information: See page 10. SONET/SDH Low-jitter clock generation xDSL Optical modules 10 GbE LAN/WAN Clock and data recovery Pin Assignments: See page 9. Description The Si552 dual-frequency VCXO utilizes Silicon Laboratories advanced (Top View) DSPLL circuitry to provide a very low jitter clock for all output frequencies. The Si552 is available with any-rate output frequency from 10 to 945 MHz V V C 1 6 DD and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a different crystal is required for each output frequency, the Si552 uses one FS 2 5 CLK fixed crystal frequency to provide a wide range of output frequencies. This IC-based approach allows the crystal resonator to provide exceptional GND 3 4 CLK+ frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si552 IC-based VCXO is factory-configurable for a wide variety of user specifications including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram V DD CLK- CLK+ Any-rate Fixed 101400 MHz Frequency XO DSPLL Clock Synthesis ADC V FS GND C Rev. 1.1 4/13 Copyright 2013 by Silicon Laboratories Si552Si552 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Units 1 V 3.3 V option 2.97 3.3 3.63 V Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 V Supply Current I Output enabled DD LVPECL 130 120 CML 108 117 mA 99 LVDS 108 90 CMOS 98 Tristate mode 60 75 mA 2 Frequency Select (FS) V 0.75 x V V IH DD V 0.5 V IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See Section 3.Ordering Informatio on page 10 for further details. 2. FS pin includes a 17 k resistor to VDD. Table 2. V Control Voltage Input C Parameter Symbol Test Condition Min Typ Max Units 1,2,3 K 10 to 90% of V 33 ppm/V Control Voltage Tuning Slope V DD 45 90 135 180 356 4 L BSL 5 1 +5 % Control Voltage Linearity VC Incremental 10 5 +10 % BW 9.3 10.0 10.7 kHz Modulation Bandwidth Z 500 k V Input Impedance VC C V f V /2 V Nominal Control Voltage CNOM O DD V 0V V Control Voltage Tuning Range C DD Notes: 1. Positive slope selectable option by part number. See Section 3.Ordering Informatio on page 10. 2. For best jitter and phase noise performance, always choose the smallest K that meets the applications minimum APR V requirements. See AN266: VCXO Tuning Slope (K ), Stability, and Absolute Pull Range (APR) for more information. V 3. K variation is 10% of typical values. V 4. BSL determined from deviation from best straight line fit with V ranging from 10 to 90% of V . Incremental slope C DD determined with V ranging from 10 to 90% of V . C DD 2 Rev. 1.1