Ultra Series Crystal Oscillator (VCXO) Si569 Data Sheet Ultra Low Jitter I2C Programmable VCXO (100 fs), 0.2 to KEY FEATURES 3000 MHz I2C programmable to any frequency from 0.2 to The Si569 Ultra Series voltage-controlled crystal oscillator utilizes Sky- 3000 MHz with < 1 ppb resolution th works Solutions advanced 4 generation DSPLL technology to provide an Ultra low jitter: 100 fs RMS Typ (12 kHz 20 MHz) ultra-low jitter, low phase noise clock at any output frequency. The device is Configure up to 2 pin-selectable startup frequencies user-programmed via simple I2C commands to provide any frequency from I2C interface supports 100 kbps, 400 kbps, and 1 0.2 to 3000 MHz with <1 ppb resolution and maintains exceptionally low Mbps (Fast Mode Plus) jitter for both integer and fractional frequencies across its operating range. Excellent PSNR and supply noise immunity: 80 On-chip power supply filtering provides industry-leading power supply noise dBc Typ rejection, simplifying the task of generating low jitter clocks in noisy systems Programmable Kv (ppm/V) simplifies development that use switched-mode power supplies. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si569 uses one 3.3 V, 2.5 V and 1.8 V V supply operation from DD simple crystal and a DSPLL IC-based approach to provide the desired out- the same part number put frequency. The Si569 is factory-configurable for a wide variety of user LVPECL, LVDS, CML, HCSL, CMOS, and Dual specifications, including startup frequency, I2C address, output format, and CMOS output options OE pin location/polarity. Specific configurations are factory-programmed at 2.5x3.2, 3.2x5, 5x7 mm package options time of shipment, eliminating long lead times associated with custom oscilla- Samples available with 1-2 week lead times tors. APPLICATIONS Pin Assignments SDA 100G/200G/400G OTN, coherent optics, PAM4 7 VC 1 6 VDD 3G-SDI/12G-SDI/24G-SDI broadcast video Servers, switches, storage, search acceleration OE/FS 2 5 CLK FPGA/ASIC clocking GND 3 4 CLK+ 8 5 x 7 mm and 3.2 x 5 mm 2.5 x 3.2 mm SCL (Top View) Fixed Frequency Frequency Flexible Pin Descriptions Low Crystal DSPLL Noise Driver DCO 1 VC = Voltage Control Pin Digital Digital OSC Phase Error Phase Loop Cancellation Detector Filter 2 Selectable via ordering option Flexible Phase Error Formats, OE = Output enable FS = Frequency Select 1.8V 3.3V Fractional Operation Divider Vc ADC 3 GND = Ground Control NVM Power Supply Regulation 4 CLK+ = Clock output OE, Frequency Select Built-in Power Supply (I2C and Pin Control) Noise Rejection 5 CLK- = Complementary clock output. Not used for CMOS. 6 VDD = Power supply 7 SDA = I2C Serial Data 8 SCL = I2C Serial Clock Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 1.3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 3, 2021 1Si569 Data Sheet Ordering Guide 1. Ordering Guide The Si569 XO supports a variety of options including startup frequency, output format, and control voltage tuning slope, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in 1-2 weeks. Skyworks Solutions provides an online part number configuration utility to simplify this process. Refer to