571FDC000159DG Silicon Labs

Si570/Si571 2 10 MHZ TO 1.4 GHZ I C PROGRAMMABLE XO/VCXO Features Any programmable output Internal fixed crystal frequency frequencies from 10 to 945 MHz and ensures high reliability and low Si5602 select frequencies to 1.4 GHz aging 2 Available LVPECL, CMOS, I C serial interface LVDS, and CML outputs 3rd generation DSPLL with superior Industry-standard 5x7 mm jitter performance package 3x better frequency stability than Pb-free/RoHS-compliant SAW-based oscillators 1.8, 2.5, or 3.3 V supply Applications Ordering Information: SONET/SDH Low-jitter clock generation See page 27. xDSL Optical modules 10 GbE LAN/WAN Clock and data recovery Pin Assignments: Description See page 26. The Si570 XO/Si571 VCXO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are (Top View) user-programmable to any output frequency from 10 to 945 MHz and select SDA frequencies to 1400 MHz with <1 ppb resolution. The device is programmed 2 7 via an I C serial interface. Unlike traditional XO/VCXOs where a different NC 1 6 V DD crystal is required for each output frequency, the Si57x uses one fixed- frequency crystal and a DSPLL clock synthesis IC to provide any-frequency operation. This IC-based approach allows the crystal resonator to provide OE 2 5 CLK exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of GND 3 4 CLK+ generating low-jitter clocks in noisy environments typically found in 8 communication systems. SCL Functional Block Diagram Si570 CLK- CLK+ V DD SDA 7 OE V C 1 6 V 10-1400 MHz DD Fixed Frequency DSPLL Clock SDA XO Synthesis SCL OE 2 5 CLK Si571 only GND 3 4 CLK+ ADC 8 SCL GND Si571 V C Rev. 1.4 4/13 Copyright 2013 by Silicon Laboratories Si570/Si571Si570/Si571 2 Rev. 1.4