590BB300M000DG Silicon Labs

Si590/591 1 ps MAX JITTER CRYSTAL OSCILLATOR (XO) (10 MHZ TO 810 MHZ) Features Si5602 Available with any-frequency output Available CMOS, LVPECL, frequencies from 10 to 810 MHz LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options 3rd generation DSPLL with superior Industry Standard 5x7 and jitter performance: 1 ps max jitter 3.2x5 mm packages Better frequency stability than SAW- Pb-free/RoHS-compliant based oscillators 40 to +85 C operating Internal fundamental mode crystal temperature range ensures high reliability Ordering Information: Applications See page 8. SONET/SDH (OC-3/12/48) Test and measurement Networking Storage Pin Assignments: SD/HD SDI/3G SDI video FPGA/ASIC clock generation See page 7. Description (Top View) The Si590/591 XO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low jitter clock at high frequencies. The Si590/591 supports any frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique 1 6 V NC DD crystal is required for each output frequency, the Si590/591 uses one fixed crystal to provide a wide range of output frequencies. This IC based OE 2 5 CLK approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior GND 3 4 supply noise rejection, simplifying the task of generating low jitter clocks in CLK+ noisy environments typically found in communication systems. The Si590/591 IC based XO is factory configurable for a wide variety of user Si590 (LVDS/LVPECL/CML) specifications including frequency, supply voltage, output format, and stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. V 1 6 DD OE Functional Block Diagram NC 2 5 NC V CLK CLK+ DD GND 3 4 CLK Si590 (CMOS) 17 k * Any-rate Fixed 10810 MHz V 1 6 DD OE OE Frequency DSPLL XO Clock Synthesis NC 2 5 CLK 17 k * GND 3 4 CLK+ Si591 (LVDS/LVPECL/CML) *Note: Output Enable High/Low Options Available See Ordering Information GND Rev. 1.2 6/18 Copyright 2018 by Silicon Laboratories Si590/591Si590/591 TABLE OF CONTENTS 1. Electrical Specifications .3 2. Pin Descriptions 7 3. Ordering Information 8 4. Package Outline Drawing: 5 x 7 mm, 6-pin 9 5. PCB Land Pattern: 5 x 7 mm, 6-pin 10 6. Package Outline Drawing: 3.2 x 5 mm, 6-pin 11 7. PCB Land Pattern: 3.2 x 5 mm, 6-pin 12 8. Si590/Si591 Top Marking: 5x7mm .13 9. Si590/Si591 Top Marking: 3.2 x 5 mm 14 Revision History .15 2 Rev. 1.2