CP2120-GMR Silicon Labs

CP2120 2 SPI TO I C BRIDGE AND GPIO PORT EXPANDER 2 Input and Output Port Pins Single Chip SPI to I C Transfer 8 Pins Configurable as Push-Pull or Open-Drain Integrated clock no external clock required 1 Pin Configurable as an edge-triggered interrupt On-Chip Voltage Monitor source Slave Serial Peripheral Interface (SPI) All pins 5 V Tolerant Up to 1.0 Mbit/s Transfers INT active low interrupt pin Configurable to Least Significant Bit or Most Significant Supply Voltage of 2.7 V to 3.6 V Bit first byte transfers Typical operating current: 6.4 mA 2 I C Master Interface Package Operates at configurable rates up to 400 kHz Pb-free 20-pin QFN 255 RX and TX Data Buffers Internal Voltage Oscillator Monitor MISO 2 SDA I C SPI MOSI Controller Interface SCL Interface SCK CS Internal Registers Port Controller Edge-Triggered Eight I/O Pins Interrupt Source Figure 1. Block Diagram Rev. 1.0 Copyright 2015 by Silicon Laboratories CP2120 Not Recommended for New DesignsCP2120 2 Rev. 1.0 Not Recommended for New Designs