CP2130 SINGLE-CHIP USB-TO-SPI BRIDGE Single-Chip USB-to-SPI Bridge SPI Controller Integrated clock no external crystal required 3 or 4-wire master mode operation Integrated USB transceiver no external resistors Configurable clock rate required - 12 MHz, 6 MHz, 3 MHz, 1.5 MHz, 750 kHz, 375 kHz, Integrated 348 Byte one-time programmable ROM for 187.5 kHz, 93.75 kHz product customization Clock phase and polarity control On-chip power-on reset circuit Chip select mode and toggle On-chip voltage regulator: 3.45 V output Programmable SPI delay (post-assert, inter-byte, pre- Uses USB Bulk Mode transactions for high throughput deassert) - Configurable priority for reads and writes 11 Configurable GPIO Pins with Alternate Functions USB Peripheral Function Controller Usable as inputs, open-drain outputs, or push-pull USB Specification 2.0 compliant full-speed (12 Mbps) outputs USB suspend states supported and indicated via Up to 11 chip select outputs suspend output pins Ready-to-read pin allows for external signal to trigger SPI read operations USB Interface Ability to count edges or pulses using the Event Counter Windows 8 , 7 , Vista , and XP Up to 11 USB remote wakeup sources Open access to interface specification SPI activity indication (toggles to indicate SPI activity) Windows Libraries Configurable clock output (93.75 kHz to 24 MHz) APIs for quick application development Supply Voltage Supports Windows 8 , 7 , Vista , and XP (SP2 & Self powered (regulator disabled): 3.0 to 3.6 V SP3) Self powered (regulator enabled): 3.0 to 5.25 V USB bus powered: 4.0 to 5.25 V Packages I/O voltage: 1.8 V to V RoHS-compliant 24-QFN package (4x4 mm) DD Ordering Part Numbers CP2130-F01-GM Temperature Range: 40 to +85 C CP2130 VREGIN MISO Connect to VBUS Voltage 48 MHz To SPI MOSI or External Supply VDD SPI Controller Regulator Oscillator Slave SCK Devices GND USB Connector USB Interface Multi-Function VBUS VBUS Signals D+ D+ Full-Speed Peripheral GPIO GPIO.0 CS0 D- 12 Mbps Function D- GPIO.1 CS1 SPI Chip Select Transceiver Controller GPIO.2 CS2 GND SPI ReadyToRead GPIO.3 CS3 RTR Multi- GPIO.4 CS4 EVTCNTR Function SPI Event Counter GPIO.5 CS5 CLKOUT Signals to RESET Clock Output GPIO.6 CS6 Hardware Reset External 348 Byte PROM GPIO.7 CS7 VPP SPI Activity Circuitry GPIO.8 CS8 SPIACT (Product Customization) GPIO.9 CS9 SUSPEND USB Suspend GPIO.10 CS10 SUSPEND Logic Level Remote Wakeup VIO I/O Power and Logic Levels Supply (1.8 V to VDD) Figure 1. Example System Diagram Rev. 0.7 1/14 Copyright 2014 by Silicon Laboratories CP2130 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Not Recommended for New DesignsCP2130 2 Rev. 0.7 Not Recommended for New Designs