EM341 High-Performance, Integrated RF4CE System-on-Chip Features Exceptional RF Performance - 32-bit ARM Cortex -M3 processor - Normal mode link budget up to 103 dB configurable up to 110 dB - 2.4 GHz IEEE 802.15.4-2003 transceiver & lower MAC - 100 dBm normal RX sensitivity configurable to - 128 kB flash, with optional read protection 102 dBm (1% PER, 20 byte packet) - 12 kB RAM memory - +3 dB normal mode output power configurable up to - AES128 encryption accelerator +8 dBm - Flexible ADC, UART/SPI/TWI serial communications, - Robust Wi-Fi and Bluetooth coexistence and general purpose timers - 24 highly configurable GPIOs with Schmitt trigger inputs Innovative network and processor debug - Packet Trace Port for non-intrusive packet trace with Industry-leading ARM Cortex -M3 processor Ember development tools - Leading 32-bit processing performance - Serial Wire/JTAG interface - Highly efficient Thumb-2 instruction set - Standard ARM debug capabilities: Flash Patch & Break- - Operation at 6, 12, or 24 MHz point Data Watchpoint & Trace Instrumentation Trace - Flexible Nested Vectored Interrupt Controller Macrocell Low power consumption, advanced management Application Flexibility - RX Current (w/ CPU): 26 mA - Single voltage operation: 2.13.6 V with internal 1.8 and - TX Current (w/ CPU, +3 dBm TX): 31 mA 1.25 V regulators - Low deep sleep current, with retained RAM and GPIO: - Optional 32.768 kHz crystal for higher timer accuracy 400 nA without/800 nA with sleep timer - Low external component count with single 24 MHz - Low-frequency internal RC oscillator for low-power sleep crystal timing - Support for external power amplifier - High-frequency internal RC oscillator for fast (110 s) - Small 7x7 mm 48-pin QFN package processor start-up from sleep TX ACTIVE Data Program PA select RAM Flash RF TX ALT P,N PA 12 kB 128 kB SYNTH DAC MAC PA + TM nd Baseband ARM Cortex -M3 2 level RF P,N LNA IF ADC CPU with NVIC Interrupt and MPU controller Packet Trace Bias CPU debug Encryption OSCA TPIU/ITM/ HF crystal Internal HF Calibration acclerator FPB/DWT OSC RC-OSC ADC General OSCB purpose Always 1.25V timers VDD CORE Powered Regulator Serial SWCLK, Domain Wire and 1.8V JTCK GPIO VREG OUT JTAG Regulator registers Watchdog debug General Purpose nRESET POR ADC UART/ SPI/TWI Chip Sleep LF crystal Internal LF manager timer OSC RC-OSC GPIO multiplexor switch PA 7:0 , PB 7:0 , PC 7:0 Rev 1.0 8/14 Copyright 2014 by Silicon Laboratories EM341 Not Recommended for New DesignsEM341 Table of Contents 1. Typical Application..............................................................................................................4 2. Electrical Specifications......................................................................................................7 2.1. Absolute Maximum Ratings............................................................................................7 2.2. Recommended Operating Conditions ............................................................................7 2.3. Environmental Characteristics........................................................................................8 2.4. DC Electrical Characteristics..........................................................................................8 2.5. Digital I/O Specifications ..............................................................................................13 2.6. Non-RF System Electrical Characteristics ...................................................................14 2.7. RF Electrical Characteristics ........................................................................................15 3. Functional Description......................................................................................................21 4. Radio Module .....................................................................................................................24 4.1. Receive (RX) Path........................................................................................................24 4.2. Transmit (TX) Path.......................................................................................................24 4.3. Calibration ....................................................................................................................24 4.4. Integrated MAC Module ...............................................................................................25 4.5. Packet Trace Interface (PTI) ........................................................................................25 4.6. Random Number Generator.........................................................................................25 5. ARM Cortex-M3 and Memory Modules ......................................................................26 5.1. ARM Cortex-M3 Microprocessor............................................................................26 5.2. Embedded Memory......................................................................................................26 5.3. Memory Protection Unit................................................................................................32 6. System Modules.................................................................................................................33 6.1. Power Domains............................................................................................................34 6.2. Resets ..........................................................................................................................35 6.3. Clocks...........................................................................................................................38 6.4. System Timers .............................................................................................................43 6.5. Power Management .....................................................................................................44 6.6. Security Accelerator .....................................................................................................47 7. GPIO (General Purpose Input/Output) .............................................................................48 7.1. GPIO Ports...................................................................................................................49 7.2. Configuration................................................................................................................49 7.3. Forced Functions..........................................................................................................50 7.4. Reset............................................................................................................................50 7.5. Boot Configuration........................................................................................................51 7.6. GPIO Modes.................................................................................................................51 7.7. Wake Monitoring ..........................................................................................................52 7.8. External Interrupts........................................................................................................53 7.9. Debug Control and Status............................................................................................54 7.10.GPIO Signal Assignment Summary.............................................................................55 7.11.Registers......................................................................................................................56 8. Serial Controllers...............................................................................................................68 8.1. Overview ......................................................................................................................68 8.2. Configuration................................................................................................................69 8.3. SPISlave Mode.........................................................................................................74 2 Rev 1.0 Not Recommended for New Designs