Si3000SSI-EVB EVALUATION BOARD FOR THE SI3000 WITH THE STANDARD SERIAL INTERFACE Description Features The Si3000SSI-EVB provides the modem system The Si3000SSI-EVB includes the following: designer an easy way to evaluate the Si3000 solution. RJ-11 Interface to Handset Power is supplied through two terminal blocks, V and D RJ-11 Connections to Phone Line and Modem V . This allows for 5-V or 3.3-V operation of the A Microphone, Speaker Interfaces evaluation board. Line In, Line out Interfaces Buffered Digital I/O Interface to DSP or ASIC Recommended Layout for Key Components Easy Power Connection for 5 V or 3.3 V Operation Easy Power Connection for Handset Flexible MCLK Scheme User Selectable Serial Mode Support for Daisy Chain Operation MotherboardDaughter Card Connection Function Block Diagram 12 Volts Motherboard VD Supply Master Board Daughter Card Line RJ11 Speaker Mic Modem Out In Phone DSP or Line ASIC Si3000 Handset Select HandSet Digital Line Line I/O Out In Motherboard to Master Line Level External I/O Daughterboard Board Audio I/O Preliminary Rev. 0.7 1/99 Copyright 1999 by Silicon Laboratories Si3000SSI-EVB-07Si3000SSI-EVB Clock Generation Functional Description The Si3000 requires an MCLK input. The EVB provides The Si3000SSI-EVB provides an easy way to evaluate two options for this requirement. MCLK can be provided the Si3000 solution. via pin 1 of JP4 (on the motherboard) from the target This Si3000 device also supports the connection of system or from an oscillator installed in Y1 (on the multiple devices on a single serial interface. The motherboard). JP3 (on the motherboard) selects the evaluation board provides a straight forward means of MCLK source to the Si3000. In the Y1 position, the evaluating this feature. oscillator installed in Y1 is connected. If 3.3 V is the VD supply, Y1 must be a V 3.3 oscillator. In the JP4 The evaluation board consists of the Si30xxSSI-EVB position, the clock on JP4 is connected. Valid MCLK motherboard Figure 8/Figure 9 and the Si3000DC-EVB frequency ranges from 1 to 60 MHz. daughter card Figure 3/Figure 4. The Si30xxSSI-EVB can be used with other Silicon Laboratories daughter If multiple boards are cascaded together, refer to the cards, such as the Si3034DC-EVB. Contact a Silicon section on daisy-chain operation. Only the master board Laboratories representative for more information. will need an MCLK from Y1 or JP4. In this document, the Si3000DC-EVB is occasionally Optional Call Progress Speaker referred to daughter card, and the Si30xxSSI-EVB as This feature on the Si30xxSSI-EVB is used in conjunc- the motherboard. The Si3000SSI-EVB refers to the tion with the Si3034/35 evaluation boards, but is not uti- system which consists of both the motherboard and lized by the Si3000. daughter card. MotherboardDaughter Card Connection Reset Circuit The Si3000 requires an active low pulse RESETon JP1 and JP2 on the daughter card are used to connect following power up and whenever all registers need to to the motherboard. be reset. Typically, the target system generates this JP1 is a 3x8 socket connection to the digital signals of signal and supplies it on pin 9 of JP4 (on the the Si3000. In addition, the V power of the D motherboard). For development purposes, the motherboard (J2) is routed to this socket and supplies Si3000SSI-EVB includes a reset push button, SW1, that the power to the daughter card. JP1 connects to JP7 of is a logic OR (active low) wth i the reset signal from the the motherboard. target system. U4 (of the motherboard) provides the JP2 is a 2x5 socket connection to the Tip and Ring and reset logic and serves as a buffer. This circuit is not chassis ground of the line interface to the handset necessary in a production design. selection circuitry. JP2 connects to JP8 of the If multiple EVBs are cascaded together, the reset signal Si30xxSSI-EVB. should be generated by the master board. Using the SW1 pushbutton on slave boards will only reset that Power Supply slave board and slave boards further down the chain. Power is supplied to the Si3000SSI-EVB by means of J2, on the motherboard, when the board is used Serial in Modes stand-alone mode. If multiple boards are cascaded The Si3000 supports two different serial modes for a together, refer to the section on daisy-chain operation glueless interface to many standard DSP and ASIC for the power supply requirements. serial ports. The serial mode of the Si3000 can be J2 is a euroblock header which allows for connection to selected by JP1 and JP2 on the motherboard. a bench power supply. J2 provides the power for all devices connected to the V node. D Table 1: Si3000 Serial Modes J2 can nominally be 3.3 V or 5 V. Note that U3 and U4 can operate from either 3.3 V or 5 V. If Y1 is used, it M1 M0 Mode must support 3.3 V operation if V = 3.3 V. D GND GND FSYNC frames data J3 is used to supply power to V. However, V is not A A GND V FSYNC pulse starts data frame D used in conjunction with the Si3000DC-EVB. V GND Slave Operation Diodes D4 and D5 on the motherboard are used to D protect the Si3000SSI-EVB ainst ag over-voltage or V V Reserved D D accidental terminal reversal. They are rated at 6.8 V. 2 Rev. 0.7