Si5020-EVB EVALUATION BOARD FOR Si5020 SiPHY MULTI-RATE SONET/SDH CLOCK AND DATA RECOVERY IC Description Features The Si5020 evaluation board provides a platform for Single 2.5 V power supply testing and characterizing Silicon Laboratories Si5020 Differential I/Os ac coupled SiPHY multi-rate SONET/SDH clock and data Simple jumper configuration recovery IC. The Si5020 CDR supports OC-48/12/3, STM-16/4/1, Gigabit Ethernet, and 2.7 Gbps FEC rates. All high-speed I/Os are AC coupled to ease interfacing to industry standard test equipment. Function Block Diagram Jitter Analyzer + Z = 50 Z = 50 + C C Pulse REFCLK CLKOUT Generator Z = 50 Z = 50 C C Si5020 Scope Z = 50 Z = 50 + + C C Pattern DATAIN DATAOUT Generator Z = 50 Z = 50 C C Pattern Analyzer RATESEL0 LOL RATESEL1 REXT PWRDN/CAL 10 k Test Point Jumpers Si5020-EVB Rev C Rev. 1.0 12/02 Copyright 2016 by Silicon Laboratories Si5020-EVB-10Si5020-EVB To improve the DATAOUT eye-diagram, short 100 Functional Description transmission line segments precede the 50 high- The evaluation board simplifies characterization of the speed traces. These segments increase the interface Si5020 Clock and Data Recovery (CDR) device by bandwidth from the chip to the 50 traces and reduce providing access to all of the Si5020 I/Os. Device data inter-symbol-interference. Please refer to Silicon performance can be evaluated by following the Test Laboratories application note AN43 for more details. Configuration section below. Specific performance Note: The 50 termination is for each terminal/side of a dif- metrics include jitter tolerance, jitter generation, and ferential signal, thus the differential termination is actu- jitter transfer. ally 50 +50 =100 . Power Supply REFCLK The evaluation board requires one 2.5 V supply. Supply REFCLK is used to center the frequency of the filtering is placed on the board to filter typical system DSPLL so that the device can lock to the data. Ideally noise components, however, initial performance testing the REFCLK frequency should be 1/128th, 1/32nd, or should use a linear supply capable of supplying 2.5 V 1/16th the VCO frequency and must have a frequency 5% dc. accuracy of 100PPM. Internally, the CDR CAUTION: The evaluation board is designed so that the automatically recognizes the REFCLK frequency within body of the SMA jacks and GND are shorted. Care must one of these three frequency ranges. Typical REFCLK be taken when powering the PCB at potentials other frequencies are given in Table1. REFCLK is AC than GND at 0.0 V and VDD at 2.5 V relative to chassis coupled to the SMA jacks located on the top side of the GND. evaluation board. Self-Calibration Table 1. Typical REFCLK Frequencies The Si5020 device provides an internal self-calibration function that optimizes the loop gain parameters within Ratio of TM SONET/ the internal DSPLL . Self-calibration is initiated by a Gigabit SDH with SONET/SDH VCO to high-to-low transition of the PWRDN/CAL signal while a Ethernet valid reference clock is supplied to the REFCLK input. 15/14 FEC REFCLK On the Si5020-EVB board, a voltage detector IC is 19.44 MHz 19.53 MHz 20.83 MHz 128 utilized to initiate self-calibration. The voltage detector drives the PWRDN/CAL signal low after the supply 77.76 MHz 78.125 MHz 83.31 MHz 32 voltage has reached a specific voltage level. This circuit 155.52 MHz 156.25 MHz 166.63 MHz 16 is described in Silicon Laboratories application note AN42. On the Si5020-EVB, the PWRDN/CAL signal is RATESEL also accessible via a jumper located in the lower left- RATESEL is used to configure the CDR to recover clock hand corner of the evaluation board. PWRDN/CAL is and data at different data rates. RATESEL is a two bit wired to the signal post adjacent to the 2.5 V post. binary input that is controlled via two jumpers located in Device Powerdown the lower left-hand corner of the evaluation board. The CDR can be powered down via the PWRDN/CAL RATESEL0/1 are wired to the center posts (signal post) signal. When asserted the evaluation board will draw between 2.5 V and GND. For example, the OC-48 data minimal current. PWRDN/CAL is controlled via one rate is selected by jumping RATESEL0 to 0.0 V and jumper located in the lower left-hand corner of the RATESEL1 to 0.0 V. evaluation board. PWRDN/CAL is wired to the signal The table given on the evaluation board lists post adjacent to the 2.5 V post. approximate data rates for the jumper configurations CLKOUT, DATAOUT, DATAIN shown in Figure 1. Applications with data rates within 7% of the given data rate are also accommodated. These high-speed I/Os are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the end- launch SMA jacks as labeled on the PCB. These I/Os are AC coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential both the positive (+) and negative () terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 resistors. 2 Rev. 1.0