Si50x-32x4-EVB EVALUATION BOARD FOR THE Si50X 3.2X4.0 MM SILICON OSCILLATORS Si50x samples should be ordered at the same time as Description the Si50x-32x4-EVB since the EVB does not come with This document describes the operation of the Skyworks the device. This allows end users maximum flexibility. Solutions Si50x-32x4-EVB Rev 2.0 evaluation board to Skyworks Solutions can solder down samples when evaluate Skyworks Solutions Si50x Silicon Oscillators ordering an EVB please specify when ordering. in the 3.2x4.0 mm package. Devices currently available include the single-ended output Si500S and the Features differential output Si500D. The Si50x utilizes Skyworks Solutions ultra stable silicon oscillator technology to Evaluation of Skyworks Solutions Si50x devices achieve an inexpensive low jitter clock source. This Stuffing options support dc or ac coupled single- unique oscillator technology is factory programmed to ended or differential output clocks support any frequency between 900 kHz and 200 MHz. Supports output signal formats: CMOS, HCSL, Unlike traditional XOs that require a unique quartz Low Power LVPECL, LVDS, LVPECL, or SSTL crystal resonator to generate each frequency, the Si50x Jumper selections for OE and MODE (reserved for uses programmable, compensated silicon oscillator future use) architecture that is capable of operating over a wide range of output frequencies. In addition, Skyworks Solutions compensated silicon oscillator provides stability comparable to fixed frequency crystal based oscillators. The Si50x is factory configurable for a wide variety of user specifications including frequency, supply voltage, output format, output drive strength, and OE behavior. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Functional Block Diagram Power Input CLK+ Configuration Output DC Si50x Jumpers Bias Block Device CLK- Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 10, 2021 Si50x-32x4-EVB 1.3. Preparing the EVB 1. Functional Description By default, the evaluation board is set up to support ac- The Si50x-32x4-EVB provides access to all I/O signals coupling of differential mode configured devices (i.e., for configuring, operating, and testing the device. Low Power LVPECL, LVDS, and SSTL). The stuffing Jumpers and test points are provided as described variations for the supported output modes are tabulated below. in Table 1. 1.1. Power Supply Table 1. Stuffing Variations The Si50x supports operation from nominal voltages of 1.8, 2.5, and 3.3 V. Supply VDD and GND are wired in Driver R1, R4 C2, C3 J2, J4 Instrument at the J1 terminals. Review the device data sheet and Termination part number for allowed configurations of output buffer CMOS empty empty empty Active scope type and device power supply. * probes 1.2. Jumpers HCSL empty 0.1 F filled HI-Z The jumpers at JP1 and JP2 allow one to pull up or pull Low Power empty 0.1 F filled 50 down OE or MODE to VDD or GND. (The MODE signal LVPECL is reserved for future use. It is not used by either the Si500S or the Si500D.) The current silkscreen for these LVDS empty 0.1 F filled 50 jumpers is reproduced in Figure 1. LVPECL 2.5 V 100 0.1 F filled 50 LVPECL 3.3 V 200 0.1 F filled 50 SSTL empty 0.1 F filled 50 *Note: Use of Coax and 50 termination produces good signal integrity but incorrect signal levels and power use of Coax and Hi-Z produces extremely bad signal Figure 1. Jumpers Silkscreen integrity. Pins 1 and 2 in Figure 1 refer respectively to the Si50x s OE and MODE pins. The jumper positions are 1.3.1. LVPECL Biasing illustrated in Figure 2. Because the Si50x can support an LVPECL buffer type The Si50x can be ordered with the OE pin pulled to the (in addition to CMOS, HCSL, LVDS, or SSTL), pulldown desired state, so the JP1 jumper would typically be resistor locations (R1 and R4) are available for proper needed only to access the opposing state. output biasing. For LVPECL buffers, correct biasing can be achieved through a variety of equivalent circuits the Si50x-32x4-EVB allows for a commonly used approximation using pulldown resistors. After the output biasing, the high-speed outputs are dc-blocked for JP1, Force OE high connection to differently biased inputs such as standard test equipment. 1.4. Test Points JP1, Force OE low There are 4 through-hole test points as follows: TP1VDD TP2Output CLK N JP2, Force Mode high TP3GND TP4Output CLK Test point TP1 is located near terminal J1. Test points TP2TP4 are located in between the output connectors. JP2, Force Mode low Figure 2. JP1JP2 Jumper Positions 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.2 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 10, 2021