Si53301/4-EVB Si53301/4 EVALUATION BOARD USERS GUIDE Description EVB Features The Si53301/4-EVB is used for evaluation of the Features of this evaluation board include: Si533xx family of low-jitter clock buffers/level Power supply connections for VDD, VDDOA and translators. As shipped from the factory, this evaluation VDDOB, GND board has the Si53301 device installed. The entire Jumpers for selection of output signal format, output Si533xx family of buffers use the same input circuits and enable, input clock select and output divider output drivers, and all have the same jitter Jumpers to allow self biasing of CMOS single-ended specifications. Thus, this evaluation board can be used inputs to evaluate any Si533xx device. The Si53301 provides SMA connectors for easy access to test and pin-selectable clock output signal format, drive strength evaluate the Si53301 control, optional clock division, and per-bank output enable. The Si53304 provides pin-selectable clock output signal format, drive strength control, and individual output enable pins for each clock output. Figure 1. Si53301/4 Evaluation Board Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 12, 2021 1. Supply Voltage Three supply voltages are required: VDD, VDDOA, and VDDOB. These supply voltages are applied at the two bottom corners of the evaluation board via J18 and J20, which are located on the bottom side of the evaluation board and function as standoffs as well as inputs for the supply voltages. Note that the J18 and J20 have silkscreen on the top side of the evaluation board that identifies the J18 and J20 inputs. VDD powers the input buffers, mux, and dividers. VDDOA and VDDOB provide power for the output drivers on CLK0,1,2 and CLK3,4,5, respectively. The three input power supply voltages should all have a common external ground. A separate ground wire should be run from the common power ground to the ground on both J18 and J20. VDD, VDDOA, and VDDOB can be 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%. VDDOA,B need to be set according to the output driver format as shown in Table 1. 2. Clock Inputs This evaluation board accepts differential clock inputs on SMA connectors labeled CLK0,CLK0B as well as CLK1,CLK1B. A single-ended CMOS input with the same voltage swing as the VDD voltage may also be applied to either CLK0 and/or CLK1. See 4.4. Jumpers P1 and P2 for more information. The clock input that is active is selected by JP1, which controls the CLK SEL input pin 8. 3. Clock Outputs Six clock outputs are present at the SMA connectors labeled Q0, 1, 2, 3, 4, 5. As built and delivered, the evaluation board will support differential outputs that are LVDS, CML, or low-power LVPECL without any component changes. Standard LVPECL and HCSL outputs require output resistor and/or capacitor changes. See the table in Figure 3 for these changes. 4. Jumpers This evaluation board can be used to evaluate a Si53301 or Si53304 however, the Si53301 is installed on the evaluation board. Refer to Figures 1, 2, and 3 and Tables 1 and 2 as needed for the following discussion about the jumpers. Many of the inputs are shown on the evaluation board silkscreen and schematic with dual names, such as name1(name2), where name1 is the input pin name for the Si53301 and name2 is the input pin name for the Si53304. In two cases, the input pin of the Si53301 is a no-connect (NC) when the Si53304 is a functional input. 4.1. Jumpers JP2 and JP3 Jumpers JP2 and JP3 set the level to SFOUTA1 and SFOUTA0 on input pins 2 and 3, respectively. Jumpers JP4 and JP5 set the level to SFOUTB1 and SFOUTB0 on input pins 22 and 23, respectively. These inputs have three valid input levels: Ground, VDD, and Open. See Table 1. 4.2. Jumpers JP1 and JP6 For the Si53301 device, Jumpers JP1 and JP6 control the output dividers for bank A (Q0,1,2) and bank B (Q3,4,5), respectively. For the Si53304 device, Jumpers JP1 and JP6 control the enabling of output clocks Q1 and Q5, respectively. See Table 2 for the settings of these jumpers. 4.3. Jumpers P3, P4, P5, P6, and P7 For the Si53301, these jumpers control CLK SEL, OEA, and OEB. OEA is the enable for output clocks Q0,1,2, and OEB is the enable for output clocks Q3,4,5. For the Si53304, these jumpers control CLK SEL, OE1, OE2, OE3, and OE4. See Table 3 for more information. 4.4. Jumpers P1 and P2 Jumpers P1 and P2 should be left open unless a single-ended input is applied to the CLK0 or CLK1 input. When a jumper is placed across P1 (P2), the voltage from the VREF pin 17 is applied to the CLK0B (CLK1B) input pin so that a CMOS input with a voltage swing of VDD (pin7) volts can be applied to the CLK0 (CLK1) pin. In addition, some resistor and capacitor changes (described in the Figure 3 schematic near P1 and P2) must be made to the evaluation board. 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 12, 2021