2 SiT1532 Smallest Footprint (1.2 mm ) CSP 10 ppm Ultra-Low Power 32.768 kHz XTAL Replacement Features Applications Smallest footprint in chip-scale (CSP): 1.5 x 0.8 mm Mobile Phones Fixed 32.768 kHz Tablets <10 ppm frequency tolerance Health and Wellness Monitors Ultra-low power: <1 A Fitness Watches Directly interfaces to XTAL inputs Sport Video Cams Supports coin-cell or super-cap battery backup voltages Wireless Keypads Vdd supply range: 1.5 V to 3.63 V over -40C to +85C Ultra-Small Notebook PC Oscillator output eliminates external load caps Pulse-per-Second (pps) Timekeeping Internal filtering eliminates external Vdd bypass cap RTC Reference Clock NanoDrive programmable output swing for lowest power Battery Management Timekeeping Pb-free, RoHS and REACH compliant Electrical Specifications Table 1. Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Frequency and Stability Fixed Output Frequency Fout 32.768 kHz Frequency Stability 1 F tol 10 ppm T = 25C, post reflow, Vdd: 1.5 V 3.63 V Frequency Tolerance A 20 ppm T = 25C, post reflow with board-level underfill, A Vdd: 1.5 V 3.63 V 2 F stab 75 ppm T = -10C to +70C, Vdd: 1.5 V 3.63 V Frequency Stability A 100 T = -40C to +85C, Vdd: 1.5 V 3.63 V A 250 T = -10C to +70C, Vdd: 1.2 V 1.5 V A 25C Aging -1 1 ppm 1st Year Supply Voltage and Current Consumption Operating Supply Voltage Vdd 1.2 3.63 V T = -10C to +70C A 1.5 3.63 V T = -40C to +85C A 3 Idd 0.90 A T = 25C, Vdd: 1.8 V. No load Core Operating Current A 1.3 T = -10C to +70C, Vdd max: 3.63 V. No load A 1.4 T = -40C to +85C, Vdd max: 3.63 V. No load A 3 Idd out 0.065 0.125 A/Vpp T = -40C to +85C, Vdd: 1.5 V 3.63 V. No load Output Stage Operating Current A t Vdd Power-Supply Ramp 100 ms Vdd Ramp-up from 0 to 90%, T = -40C to +85C A Ramp 4 t start 180 300 ms Start-up Time at Power-up T = -40C T +50C, valid output A A 450 T = +50C < T +85C, valid output A A Operating Temperature Range Commercial Temperature T use -10 70 C Industrial Temperature -40 85 C Notes: 1. Measured peak-to-peak. Tested with Agilent 53132A frequency counter. Due to the low operating frequency, the gate time must be 100 ms to ensure an accurate frequency measurement. 2. Measured peak-to-peak. Inclusive of Initial Tolerance at 25C, and variations over operating temperature, rated power supply voltage and load. Stability is specified for two operating voltage ranges. Stability progressively degrades with supply voltage below 1.5 V. 3. Core operating current does not include output driver operating current or load current. To derive total operating current (no load), add core operating current + (0.065 A/V) * (output voltage swing). 4. Measured from the time Vdd reaches 1.5 V. Rev 1.28 3 March 2021 www.sitime.com 2 SiT 1532 Smallest Footprint (1.2 mm ) CSP, 10 ppm Ultra-Low Power 32.768 kHz XTAL Replacement Table 1. Electrical Characteristics (continued) Parameter Symbol Min. Typ. Max. Unit Condition LVCMOS Output Option, T = -40C to +85C, typical values are at T = 25C A A 100 200 10-90% (Vdd), 15 pF load, Vdd = 1.5 V to 3.63 V Output Rise/Fall Time tr, tf ns 50 10-90% (Vdd), 5 pF load, Vdd 1.62 V Output Clock Duty Cycle DC 48 52 % Vdd: 1.5V 3.63V. I = -10 A, 15 pF Output Voltage High VOH 90% V OH Output Voltage Low VOL 10% V Vdd: 1.5V 3.63V. I = 10 A, 15 pF OL NanoDrive Programmable, Reduced Swing Output Output Rise/Fall Time tf, tf 200 ns 30-70% (V /V ), 10 pF Load OL OH Output Clock Duty Cycle DC 48 52 % SiT1532 does not internally AC-couple. This output description 0.20 to is intended for a receiver that is AC-coupled. See Table 5 for AC-coupled Programmable Output V sw V acceptable NanoDrive swing options. Swing 0.80 Vdd: 1.5 V 3.63 V, 10 pF Load, I / I = 0.2 A. OH OL 0.60 to Vdd: 1.5 V 3.63 V. I = -0.2 A, 10 pF Load. See Table 4 DC-Biased Programmable Output OH VOH V Voltage High Range 1.225 for acceptable V /V setting levels. OH OL 0.35 to Vdd: 1.5 V 3.63 V. I = 0.2 A, 10 pF Load. See Table 4 DC-Biased Programmable Output OL VOL V Voltage Low Range 0.80 for acceptable V /V setting levels. OH OL Programmable Output Voltage T = -40C to +85C, Vdd = 1.5 V to 3.63 V. -0.055 0.055 V A Swing Tolerance Jitter ns Cycles = 10,000, T = 25C, Vdd = 1.5 V 3.63 V Period Jitter T jitt 35 A RMS Table 2. Pin Configuration Pin Symbol I/O Functionality CSP Package (Top View) Power Supply Connect to ground. Acceptable to connect pin 1 and 4 together. 1, 4 GND Ground Both pins must be connected to GND. GND GND 1 4 Oscillator clock output. The CLK can drive into a Ref CLK input or into an ASIC or chip-sets 32kHz XTAL input. When driving into an ASIC or chip-set oscillator input (X IN and X Out), the CLK Out is 2 CLK Out OUT typically connected directly to the XTAL IN pin. No need for load capacitors. The output driver is intended to be insensitive to capacitive loading. 2 3 CLK Out Vdd Connect to power supply 1.2 V Vdd 3.63 V. Under normal operating conditions, Vdd does not require external bypass/decoupling capacitor(s). Figure 1. Pin Assignments Power For more information about the internal power-supply filtering, see 3 Vdd Supply the Power Supply Noise Immunity section in the detailed description. Contact factory for applications that require a wider operating supply voltage range. Rev 1.28 Page 2 of 12 www.sitime.com