PRELIMINARY SiT1568 2 1.2 mm Power, 5 ppm, 32.768 kHz TCXO with In-System Auto-Calibration Features Applications 32.768 kHz 5 ppm all-inclusive frequency stability Smart watches, health and wellness monitors In-system auto-calibration: Ultra-accurate RTC reference clock Compensates for board-level stress-induced frequency errors Smart utility meters, E-meters Improves all-inclusive frequency stability Internet of Things (IoT) 2 Worlds smallest TCXO Footprint: 1.2 mm 1.5 x 0.8 mm CSP No external bypass cap required Drives multiple loads and eliminates multiples XTALs Low integrated phase jitter (IPJ) suitable for multiplying up for portable audio: 2.5ns RMS Ultra-low power: 4.5 A Supply voltage: 1.8V 10% Operating temperature ranges: -20C to +70C, -40C to +85C Pb-free, RoHS and REACH compliant Electrical Characteristics Table 1. Electrical Characteristics Conditions: Min/Max limits are over temperature, Vdd = 1.8V 10%, unless otherwise stated. Typicals are at 25C and Vdd = 1.8V. Parameter Symbol Min. Typ. Max. Unit Condition Frequency and Stability Output Frequency Fout 32.768 kHz F stab -5 5 ppm All inclusive, after overmold, post in-system calibration. Total Frequency Stability after 1 Overmold -25 25 ppm All inclusive, after overmold, before in-system calibration. Total Frequency Stability without All inclusive, under influence of up to 5C/sec temp -5 5 ppm 1 Overmold or Calibration gradient and board-level underfill. Allan Deviation AD 1e-8 4e-8 - 1 second averaging time. First Year Frequency Aging F aging 1 ppm T = 25C, Vdd = 1.8V, with overmold. A Jitter and Frequency Response Performance Integration bandwidth = 100 Hz to 16.384 kHz. Inclusive of Integrated Phase Jitter ns 50 mV peak-to-peak sinusoidal noise on Vdd. Noise IPJ 1.8 2.5 RMS frequency 100 Hz to 20 MHz. RMS Period Jitter PJ 2.5 4 ns RMS RMS 10,000 samples, per JEDEC standard 65B 7Peak-to-Peak Period Jitter PJp-p 20 35 nsp-p Dynamic Temperature -0.5 +0.5 ppm/sec Under temp ramp up to 1.5C/sec Frequency Response Supply Voltage and Current Consumption Operating Supply Voltage Vdd 1.62 1.8 1.98 V Supply Current Idd 4.5 5.3 A No Load. Measured when supply reaches 90% of final Vdd to the Start-up Time at Power-up t start 300 ms first output pulse. Operating Temperature Range C ordering code. -20 70 C Operating Temperature Range Op Temp I ordering code. -40 85 C LVCMOS Output Output Rise/Fall Time tr, tf 9 20 ns 10-90% (Vdd), 15 pF Load. Output Clock Duty Cycle DC 45 55 % I = -1 A Output Voltage High VOH 90% Vdd OH Output Voltage Low VOL 10% Vdd I = 1 A OL Note: 1. Contact SiTime for specific overmold conditions. Relative to 32.768 kHz, includes initial tolerance, over temp, Vdd, load, hysteresis, board-level underfill, and, 3x reflow. Tested with Agilent 53132A frequency counter. Measured with 100ms gate time for accurate frequency measurement. Rev. 1.0 March 15, 2018 www.sitime.com PRELIMINARY SiT1568 2 1.2mm Power, 5 ppm, 32.768 kHz TCXO with In-System Auto-Calibration Table 2. Pin Configuration CSP Package (Top View) CSP Pin Symbol I/O Functionality 1 Auto-Cal or Control Input Used for communicating calibration information to the chip for improving CAL/NC 1 4 GND stability in the presence of board level induced stresses. NC Leave pin floating (NC) when not using the calibration function. 2 CLK Out OUT Oscillator clock output. 3 Vdd Power Supply 1.8V 10% power supply. For most applications, the internal bypass CLK Out 2 3 Vdd filtering is acceptable. A PSNR plot is shown in the Typ Ops section. If power-supply bypassing is required, a 10-100 nF low ESR, ceramic capacitor is acceptable. Figure 1. Pin Assignment 4 GND Power Supply Connect to ground. Ground Table 3. Absolute Maximum Ratings Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameters Test Conditions Value Unit Continuous Power Supply Voltage Range (Vdd) -0.5 to 4.0 V Continuous Maximum Operating Temperature Range 105 C Human Body Model (HBM) ESD Protection JESD22-A114 2000 V Charge-Device Model (CDM) ESD Protection JESD22-C101 750 V Machine Model (MM) ESD Protection T = 25C 200 V A Latch-up Tolerance JESD78 Compliant Mechanical Shock Resistance Mil 883, Method 2002 20,000 g Mechanical Vibration Resistance Mil 883, Method 2007 70 g 1508 CSP Junction Temperature 150 C Storage Temperature -65 to 150 C System Block Diagram MEMS Resonator GND Control Regulators Vdd Temp Temp-to-Digital NVM Control Prog Prog Ultra-low Sustaining Power Cal/NC Divider Driver CLK Out Amp Frac-n PLL Figure 2. SiT1568 Block Diagram Rev. 1.0 Page 2 of 13 www.sitime.com