SiT3808 1 MHz to 80 MHz High Performance MEMS VCXO The Smart Timing Choice The Smart Timing Choice Features Applications Any frequency between 1 MHz and 80 MHz with 6 decimal places of Telecom clock synchronization, instrumentation accuracy Low bandwidth analog PLL, jitter cleaner, clock recovery, audio 100% pin-to-pin drop-in replacement to quartz-based VCXO Video, 3G/HD-SDI, FPGA, broadband and networking Frequency stability as tight as 10 ppm Widest pull range options from 25 ppm to 1600 ppm Industrial or extended commercial temperature range Superior pull range linearity of 1%, 10 times better than quartz LVCMOS/LVTTL compatible output Four industry-standard packages: 2.5 mm x 2.0 mm (4-pin), 3.2 mm x 2.5mm (4-pin), 5.0 mm x 3.2 mm (6-pin), 7.0 mm x 5.0 mm (6-pin) Instant samples with Time Machine II and field programmable oscillators RoHS and REACH compliant, Pb-free, Halogen-free and Antimony-free Electrical Specifications 1, 2, 3 Table 1. Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition Frequency Range Output Frequency Range f1 80 MHz Frequency Stability and Aging 4 Frequency Stability F stab -10 +10 ppm Inclusive of Initial tolerance at 25 C, and variation over temperature, rated supply voltage and load. -25 +25 ppm -50 +50 ppm Aging F aging -5 +5 ppm 10 years, 25C Operating Temperature Range T use -20 +70 C Extended Commercial -40 +85 C Industrial Supply Voltage and Current Consumption Supply Voltage Vdd 1.71 1.8 1.89 V Additional supply voltages between 2.5V and 3.3V can be supported. Contact SiTime for additional information. 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.97 3.3 3.63 V Current Consumption Idd 31 33 mA No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V 29 31 mA No load condition, f = 20 MHz, Vdd = 1.8V Standby Current I std 70 A Vdd = 2.5V, 2.8V, 3.3V, ST = GND, output is Weakly Pulled Down 10 A Vdd = 1.8V, ST = GND, output is Weakly Pulled Down VCXO Characteristics 5, 6 PR ppm See the Absolute Pull Range and APR table on page 10 25, 50, 100, 150, 200, Pull Range 400, 800, 1600 Upper Control Voltage VC U 1.7 V Vdd = 1.8V, Voltage at which maximum deviation is guaranteed. 2.4 V Vdd = 2.5V, Voltage at which maximum deviation is guaranteed. 2.7 V Vdd = 2.8V, Voltage at which maximum deviation is guaranteed. 3.2 V Vdd = 3.3V, Voltage at which maximum deviation is guaranteed. Lower Control Voltage VC L 0.1 V Voltage at which minimum deviation is guaranteed. Control Voltage Input Impedance Z in 100 k Control Voltage Input Capacitance C in 5 pF Linearity Lin 0.1 1 % Frequency Change Polarity Positive slope Control Voltage Bandwidth (-3dB) V BW 8 kHz Contact SiTime for 16 kHz and other high bandwidth options SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Rev. 1.01 Revised January 8, 2015SiT3808 1 MHz to 80 MHz High Performance MEMS VCXO The Smart Timing Choice The Smart Timing Choice Electrical Specifications (continued) 1, 2, 3 Table 1. Electrical Characteristics Parameter Symbol Min. Typ. Max. Unit Condition LVCMOS Output Characteristics Duty Cycle DC 4555 % All Vdds. Refer to Note 11 for definition of Duty Cycle Rise/Fall Time Tr, Tf 1.5 2 ns Vdd = 1.8V, 2.5v, 2.8V or 3.3V, 10% - 90% Vdd level Output High Voltage VOH 90% Vdd IOH = -7 mA (Vdd = 3.0V or 3.3V) IOH = -4 mA (Vdd = 2.8V or 2.5V) IOH = -2 mA (Vdd = 1.8V) Output Low Voltage VOL 10% Vdd IOL = 7 mA (Vdd = 3.0V or 3.3V) IOL = 4 mA (Vdd = 2.8V or 2.5V) IOL = 2 mA (Vdd = 1.8V) Input Characteristics Input Pull-up Impedance Z in 100 250 k For the OE/ST pin for 6-pin devices Input Capacitance C in 5 pF For the OE/ST pin for 6-pin devices Startup and Resume Timing Startup Time T start 10 ms See Figure 7 for startup resume timing diagram OE Enable/Disable Time T oe 180 ns f = 40 MHz, all Vdds. For other freq, T oe = 100 ns + 3 clock periods Resume Time T resume 7 10 ms See Figure 8 for resume timing diagram Jitter RMS Period Jitter T jitt 1.5 2 ps f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V 2 3 ps f = 20 MHz, Vdd = 1.8V RMS Phase Jitter (random) T phj 0.5 1 ps f = 20 MHz, Integration bandwidth = 12 kHz to 20 MHz, All Vdds Notes: 1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated. 2. The typical value of any parameter in the Electrical Characteristics table is specified for the nominal value of the highest voltage option for that parameter and at 25C temperature. 3. All max and min specifications are guaranteed across rated voltage variations and operating temperature ranges, unless specified otherwise 4. Initial tolerance is measured at Vin = Vdd/2 5. Absolute Pull Range (APR) is defined as the guaranteed pull range over temperature and voltage. 6. APR = pull range (PR) - frequency stability (F stab) - Aging (F aging) Rev. 1.01 Page 2 of 11 www.sitime.com