SiT5021 1-220 MHz High Performance Differential (VC) TCXO The Smart Timing Choice The Smart Timing Choice Features Applications Any frequency between 1 MHz and 220 MHz accurate to 6 decimal SATA, SAS, 10GB Ethernet, Fibre Channel, PCI-Express places Networking, broadband, instrumentation LVPECL and LVDS output signaling types 0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth Frequency stability as low as 5 ppm. Contact SiTime for tighter stability options Industrial and extended commercial temperature ranges Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2 and 7.0 x 5.0 mm For frequencies higher than 220 MHz, refer to SiT5022 datasheet Electrical Characteristics Parameter and Conditions Symbol Min. Typ. Max. Unit Condition LVPECL and LVDS, Common Electrical Characteristics Supply Voltage Vdd 2.97 3.3 3.63 V 2.25 2.5 2.75 V 2.25 3.63 V Termination schemes in Figures 1 and 2 - XX ordering code Output Frequency Range f 1 220 MHz Initial Tolerance F init -2 2 ppm At 25C after two reflows Stability Over Temperature F stab Over operating temperature range at rated nominal power supply voltage and load. -5 +5 ppm Contact SiTime for tighter stability options. Supply Voltage F vdd 50 ppb 10% Vdd Output Load F load 0.1 ppm 15 pF 10% of load First Year Aging F aging1 -2.5 +2.5 ppm 25C 10-year Aging F aging10 -5 +5 ppm 25C Operating Temperature Range T use -40 +85 C Industrial -20 +70 C Extended Commercial Pull Range PR 12.5, 25, 50 ppm Upper Control Voltage VC U Vdd-0.1 V All Vdds. Voltage at which maximum deviation is guaranteed. Control Voltage Range VC L 0.1 V Control Voltage Input Impedance Z vc 100 k Frequency Change Polarity Positive slope Control Voltage -3dB Bandwidth V BW 8 kHz Input Voltage High VIH 70% Vdd Pin 1, OE or ST Input Voltage Low VIL 30% Vdd Pin 1, OE or ST Input Pull-up Impedance Z in 100 250 k Pin 1, OE logic high or logic low, or ST logic high 2 M Pin 1, ST logic low Start-up Time T start 6 10 ms Measured from the time Vdd reaches its rated minimum value. Resume Time T resume 6 10 ms In Standby mode, measured from the time ST pin crosses Duty Cycle DC 45 55 % Contact SiTime for tighter duty cycle LVPECL, DC and AC Characteristics Current Consumption Idd 61 69 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V OE Disable Supply Current I OE 35 mA OE = Low Output Disable Leakage Current I leak 1 A OE = Low Standby Current I std 100 A ST = Low, for all Vdds Maximum Output Current I driver 30 mA Maximum average current drawn from OUT+ or OUT- Output High Voltage VOH Vdd-1.1 Vdd-0.7 V See Figure 1(a) Output Low Voltage VOL Vdd-1.9 Vdd-1.5 V See Figure 1(a) Output Differential Voltage Swing V Swing 1.2 1.6 2.0 V See Figure 1(b) Rise/Fall Time Tr, Tf 300 500 ps 20% to 80%, see Figure 1(a) OE Enable/Disable Time T oe 115 ns f = 212.5 MHz - For other frequencies, T oe = 100ns + 3 period RMS Period Jitter T jitt 1.2 1.7 ps f = 100 MHz, VDD = 3.3V or 2.5V 1.2 1.7 ps f = 156.25 MHz, VDD = 3.3V or 2.5V 1.2 1.7 ps f = 212.5 MHz, VDD = 3.3V or 2.5V RMS Phase Jitter (random) T phj 0.6 0.85 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Rev. 1.5 Revised November 12, 2015SiT5021 1-220 MHz High Performance Differential (VC) TCXO The Smart Timing Choice The Smart Timing Choice Electrical Characteristics (continued) Parameter and Conditions Symbol Min. Typ. Max. Unit Condition LVDS, DC and AC Characteristics Current Consumption Idd 47 55 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V OE Disable Supply Current I OE 35 mA OE = Low Differential Output Voltage VOD 250 350 450 mV See Figure 2 Output Disable Leakage Current I leak 1 AOE = Low Standby Current I std 100 A ST = Low, for all Vdds VOD Magnitude Change VOD 50 mV See Figure 2 Offset Voltage VOS 1.125 1.2 1.375 V See Figure 2 VOS Magnitude Change VOS 50 mV See Figure 2 Rise/Fall Time Tr, Tf 495 600 ps 20% to 80%, see Figure 2 OE Enable/Disable Time T oe 115 ns f = 212.5 MHz - For other frequencies, T oe = 100ns + 3 period RMS Period Jitter T jitt 1.2 1.7 ps f = 100 MHz, VDD = 3.3V or 2.5V 1.2 1.7 ps f = 156.25 MHz, VDD = 3.3V or 2.5V 1.2 1.7 ps f = 212.5 MHz, VDD = 3.3V or 2.5V RMS Phase Jitter (random) T phj 0.6 0.85 ps f = 156.25 MHz, Integration bandwidth = 12 kHz to 20 MHz, all Vdds Pin Description Pin Map Functionality V Control Voltage control H or Open: specified frequency output Top View VC/OE/ST Output Enable 1 L: output is high impedance H or Open: specified frequency output Standby VC/OE/ST 1 6 VDD L: Device goes to sleep mode. Supply current reduces to I std. 2 NC NA No Connect Leave it floating or connect to GND for better heat dissipation 2 5 NC OUT- 3 GND Power VDD Power Supply Ground 4 OUT+ Output Oscillator output 3 4 GND OUT+ 5 OUT- Output Complementary oscillator output 6 VDD Power Power supply voltage Absolute Maximum Attempted operation outside the absolute maximum ratings may cause permanent damage to the part. Actual performance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameter Min. Max. Unit Storage Temperature -65 150 C VDD -0.5 4 V Electrostatic Discharge (HBM) 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) 260 C Thermal Consideration JA, 4 Layer Board JC, Bottom Package (C/W) (C/W) 7050, 6-pin 142 27 5032, 6-pin 97 20 3225, 6-pin 109 20 Environmental Compliance Parameter Condition/Test Method Mechanical Shock MIL-STD-883F, Method 2002 Mechanical Vibration MIL-STD-883F, Method 2007 Temperature Cycle JESD22, Method A104 Solderability MIL-STD-883F, Method 2003 Moisture Sensitivity Level MSL1 260C Rev. 1.5 Page 2 of 8 www.sitime.com