SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice Features Applications Frequency range from 1 MHz to 110 MHz Printers LVCMOS/LVTTL compatible output Flat panel drivers Standby current as low as 0.4 A PCI Fast resume time of 3 ms (Typ) Microprocessors <30 ps cycle-to-cycle jitter Spread options (contact SiTime for other spread options) Center spread: 0.50%, 0.25% Down spread: -1%, -0.5% Standby, output enable, or spread disable mode Industry-standard packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2, 7.0 x 5.0 mm x mm Outstanding mechanical robustness for portable applications All-silicon device with outstanding reliability of 2 FIT (10x improvement over quartz-based devices), enhancing system mean-time-to-failure (MTBF) Pb-free, RoHS and REACH compliant DC Electrical Characteristics Parameters Symbol Min. Typ. Max. Unit Condition Output Frequency Range f1 110 MHz Frequency Tolerance F tol -50 +50 PPM Inclusive of: Initial stability, operating temperature, rated power, supply voltage change, load change, shock and vibration -100 +100 PPM Spread Off Aging Ag -1 1 PPM 1st year at 25C Operating Temperature Range T use -20 +70 C Extended Commercial -40 +85 C Industrial Supply Voltage Vdd 1.71 1.8 1.89 V 2.25 2.5 2.75 V 2.52 2.8 3.08 V 2.97 3.3 3.63 V Current Consumption Idd 3.7 4.1 mA No load condition, f = 20 MHz, Vdd = 2.5 V, 2.8 V or 3.3 V 3.2 3.5 mA No load condition, f = 20 MHz, Vdd = 1.8 V Standby Current I std 2.4 4.3 AST = GND, Vdd = 3.3 V, Output is Weakly Pulled Down 1.2 2.2 AST = GND, Vdd = 2.5 or 2.8 V, Output is Weakly Pulled Down 0.4 0.8 AST = GND, Vdd = 1.8 V, Output is Weakly Pulled Down Duty Cycle DC 45 55 % All Vdds. f <= 70 MHz 40 60 % All Vdds. f >70 MHz Rise/Fall Time Tr, Tf 1 2 ns 20% - 80% Vdd=2.5 V, 2.8 V or 3.3 V, 15 pf load - 1.3 2.5 ns 20% - 80% Vdd=1.8 V, 15 pf load Output Voltage High VOH 90% Vdd IOH = -4 mA (Vdd = 3.3 V) IOH = -3 mA (Vdd = 2.8 V and 2.5 V) IOH = -2 mA (Vdd = 1.8 V) Output Voltage Low 10 %Vdd IOL = -4 mA (Vdd = 3.3 V) VOL IOL = -3 mA (Vdd = 2.8 V and 2.5 V) IOL = -2 mA (Vdd = 1.8 V) Output Load Ld 15 pF At maximum frequency and supply voltage. Contact SiTime for higher output load option Input Voltage High VIH 70% Vdd Pin 1, OE or ST or SD Input Voltage Low VIL 30% Vdd Pin 1, OE or ST or SD Startup Time T start 10 ms Measured from the time Vdd reaches its rated minimum value Resume Time T resume 3.0 3.8 ms Measured from the time ST pin crosses 50% threshold Cycle-to-Cycle Jitter T cyc 26 ps f = 50 MHz, Spread = ON 26 ps f = 50 MHz, Spread = OFF SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com Rev. 1.7 Revised November 18, 2013SiT9003 Low Power Spread Spectrum Oscillator The Smart Timing Choice The Smart Timing Choice 1 Spread Spectrum Modes Center Spread Down Spread Code BD O Q 2 2 Percentage 0.25% 0.50% -0.5% -1.0% Notes: 1. In both center spread and down spread modes, triangle modulation is employed with a frequency of ~32 kHz. 2. 0.5% and -1.0% are available ONLY for <75 MHz in extended commercial temperature range. Pin Configuration Top View Pin Symbol Functionality 3 H or Open : specified frequency output Standby (ST) L: output is low (weak pull down). Oscillator stops ST/OE/SD 1 4 VDD 3 H or Open : specified frequency output 1ST/OE/SD Output Enable (OE) L: output is high impedance. H or Open: Spread = ON Spread Disable (SD) L: Spread =OFF GND 2 3 CLK 2 GND Ground Connect to Ground 3 CLK Output Clock Output 4 VDD Power Supply Note: 3. In 1.8 V mode, a resistor of <10 k between OE pin and VDD is recommended. Absolute Maximum Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor- mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings. Parameters Min. Max. Unit Storage Temperature -65 150 C VDD -0.5 4 V Electrostatic Discharge 2000 V Soldering Temperature (follow standard Pb free soldering guidelines) 260 C Number of Program Writes 1 NA Program Retention over -40 to 125C, Process, VDD (0 to 3.65V) 1,000+ years Thermal Considerations 6 Junction-to-Ambient Thermal Junction-to-Case Resistance (C/W) (bottom) Thermal Resistance 5 4 Package Lead Count Center Pad 4 Layer Board 2 Layer Board (C/W) 7050 4 Soldered down 43.6 229 2.6 7050 4 Not soldered down 191 263 2.6 7050 4 No center pad 142 273 29.8 5032 4 No center pad 96.8 199 24 3225 4 No center pad 109 212 27 2520 4 No center pad 117 222 26 Notes: 4. Test boards compliant with JESD51-3. 5. Test boards compliant with JESD51-7. 6. Referenced to bottom of case. Rev. 1.7 Page 2 of 9 www.sitime.com