DATA SHEET SKY12347-362LF: DC-3.0 GHz Six-Bit Digital Attenuator with Serial or Parallel Driver (0.5 dB LSB) Applications Cellular, 3G/4G, WiMAX, and LTE Infrastructures Features Broadband operation: DC to 3.0 GHz Attenuation: 31.5 dB with 0.5 dB LSB TTL/CMOS-compatible serial, parallel, or latched parallel control interface Single supply voltage: +3.3 or +5 V Small, QFN (24-pin, 4 x 4 mm) package (MSL1, 260 C per JEDEC J-STD-020) Figure 1. SKY12347-362LF Block Diagram Attenuation is controlled by a Serial Peripheral Interface (SPI). Depending on the SPI sequence applied to the SDI pin, the Description attenuation state between the RF1 and RF2 pins can vary between The SKY12347-362LF is a GaAs pHEMT six-bit broadband digital a low insertion loss state or up to 31.5 dB. The D0 through D5 DC attenuator with a 0.5 dB Least Significant Bit (LSB). A Transistor- control pins determine the attenuation state if parallel mode is to-Transistor Logic (TTL)/CMOS-compatible, dual-mode serial or enabled. parallel interface controller is integrated into the device. The device is provided in a 4 x 4 mm, 24-pin Quad Flat No-Lead The attenuator features low insertion loss, excellent attenuation (QFN) package. A functional block diagram is shown in Figure 1. accuracy, a 31.5 dB attenuation range, and high linearity The pin configuration and package are shown in Figure 2. Signal performance. The SKY12347-362LF is an ideal choice for a wide pin assignments and functional pin descriptions are provided in variety of cellular 3G and 4G infrastructure applications. Table 1. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 201371B Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice April 7, 2011 1 DATA SHEET SKY12347-362LF SIX-BIT DIGITAL ATTENUATOR Figure 2. SKY12347-362LF Pinout 24-Pin QFN (Top View) Table 1. SKY12347-362LF Signal Descriptions Pin Name Description Pin Name Description 1 P/S Selects serial or parallel operation. Logic 13 RF2 RF input/output to digital attenuator. low enables parallel mode. 2 CLK Serial clock input 14 GND Ground 3 SDI Serial data input 15 SDO Serial data output 4 LE On rising edge of pulse, shifts six most 16 PUP2 Sets device power-up attenuation state. See recent clocked-in bits to set attenuation Table 7. state. In parallel mode, if latch enable is logic high, changes to pins 19 to 24 occur directly. If latch enable is logic low, the attenuator does not change states until the signal is raised. 5 GND Ground 17 PUP1 Sets device power-up attenuation state. See Table 7. 6 RF1 RF input/output to digital attenuator. 18 VDD DC power supply 7 NC GND No connection. Can be grounded without 19 D5 TTL/CMOS DC control pin for parallel mode affecting performance. operation. D5 is MSB. 8 NC GND No connection. Can be grounded without 20 D4 TTL/CMOS DC control pin for parallel mode affecting performance. operation 9 NC GND No connection. Can be grounded without 21 D3 TTL/CMOS DC control pin for parallel mode affecting performance. operation 10 NC GND No connection. Can be grounded without 22 D2 TTL/CMOS DC control pin for parallel mode affecting performance. operation 11 NC GND No connection. Can be grounded without 23 D1 TTL/CMOS DC control pin for parallel mode affecting performance. operation 12 NC GND No connection. Can be grounded without 24 D0 TTL/CMOS DC control pin for parallel mode affecting performance. operation. D0 is LSB. Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 April 7, 2011 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice 201371B