SSD2828QL9 Solomon

SOLOMON SYSTECH SEMICONDUCTOR TECHNICAL DATA SSD2828 Advance Informatiom MIPI Master Bridge This document contains information on a new product. Specifications and information herein are subject to change without notice. Appendix 1: IC Revision history of SSD2828 Specification Version Change Items Effective Date st 0.10 1 Release 24-Apr-12 1.0 Initial release of Advance Information 08-Aug-12 1.1 - Remove DFR register and interface format select (IFS) description (Section 19-Sept-12 10.1) - Modify PLL calculation (Section 8.1.12) - Include example for 1 frame RAM size in command mode setting (Packet size control register ( 8.1.14)) - Modify flow for MIPI read (Section 10.5.1, 10.6.1) - Modify PS 1:0 = 11 setting (Section 7) 1.2 - Modify TX CLK pin description (Section 7) 13-Dec-12 - Modify the description of END and CO (Section 8.1.38) - Modify the timing for data latch in RGB timing (Section 14.6) 1.3 - Specify the prefix T in RGB timing (Section14.6) 09-Jan-13 SSD2828 Rev 1.3 P 2/182 Dec 2012 Solomon Systech