SPEAr600 Embedded MPU with dual ARM926 core, flexible memory support, powerful connectivity features and programmable LCD interface Datasheet production data Features Dual ARM926EJ-S core up to 333 MHz: Each with 16 Kbytes instruction cache + 16 Kbytes data cache High performance 8-channel DMA Dynamic power saving features Up to 733 DMIPS Memory: PBGA420 (23 x 23 x 2.06 mm) External DRAM interface: 8/16-bit DDR1- 2 333 / DDR2 - 666 3 x I S interfaces for audio features: 32 Kbytes BootROM / 8 Kbytes internal One stereo input and two stereo outputs SRAM (audio 3.1 configuration capable) Flexible static memory controller (FSMC) Customizable logic with 600 Kgate standard supporting parallel NAND Flash memory cell array interface, ONFI 1.0 support, internal 1-bit Software: ECC or external 4-bit ECC System compliant with all operating Serial NOR Flash Memory interface systems (including Linux) Connectivity: 2 x USB 2.0 Host Applications USB 2.0 Device Giga Ethernet (GMII port) The SPEAr embedded MPU family targets 2 I C and fast IrDA interfaces networked devices used for communication, 3 x SSP Synchronous serial peripheral display and control. This includes diverse (SPI, Microwire or TI protocol) ports consumer, business, industrial and life science applications such as: 2 x UART interfaces IP phones, thin client computers, printers, Peripherals supported: programmable logic controllers, PC TFT/STN LCD controller (resolution up to docking stations, 1024 x 768 and colors up to 24 bpp) Medical lab/diagnostics equipment, Touchscreen support wireless access devices, home appliances, Miscellaneous functions residential control and security systems, Integrated real-time clock, watchdog, and digital picture frames, and bar-code system controller scanners/readers. 8-channel 10-bit ADC, 1 Msps JPEG codec accelerator Table 1. Device summary 10 GPIO bidirectional signals with interrupt Temp. capability Order code Package Packing range 10 independent 16-bit timers with PBGA420 programmable prescaler SPEAR600-2 -40 to 85 C (23 x 23 x Tray 32-bit width External local bus (EXPI interface). 2.06 mm) May 2012 Doc ID 16259 Rev 3 1/97 This is information on a product in full production. www.st.com 1Contents SPEAr600 Contents 1 Description . 8 1.1 Main features . 9 2 Architecture overview . 11 2.1 Embedded memory units . 13 2.2 DDR/DDR2 memory controller . 13 2.3 Serial memory interface 13 2.4 Flexible static memory controller . 14 2.5 Multichannel DMA controller 15 2.6 LCD controller . 15 2.7 GPIOs . 15 2.8 JPEG codec . 16 2.9 8-channel ADC . 16 2.10 Ethernet controller 16 2.11 USB2 host controller 17 2.12 USB2 device controller . 17 2.13 Synchronous Serial Peripheral (SSP) . 18 2.14 I2C 18 2.15 UARTs . 18 2.16 Fast IrDA controller 19 2 2.17 I S audio block . 19 2.18 System controller . 19 2.18.1 Power saving system mode control 20 2.19 Clock and reset system 20 2.20 Vectored interrupt controller (VIC) 21 2.21 General purpose timers 21 2.22 Watchdog timer 22 2.23 RTC oscillator 22 2.24 Reconfigurable array subsystem connectivity (RAS) 22 2.25 External Port Controller (EXPI I/F) 23 2/97 Doc ID 16259 Rev 3