L6759D STMicroelectronics

L6759D 3+1 dual controller for VR12 with PMBus Datasheet production data Features VR12 compliant with 25 MHz SVID bus Rev1.5 SerialVID with programmable IMAX, TMAX, VBOOT, ADDRESS Second generation LTB Technology VFQFPN48 - 6x6mm Flexible driver/DrMOS support JMode support Description Fully configurable through PMBus The L6759D is a dual controller designed to Dual controller: power Intels VR12 processor memories: all 3-phase for VDDQ required parameters are programmable through 1-phase for VTT dedicated pin-strapping and PMBus interface. Single NTC design for TM, LL and Imon The device features 3-phase programmable thermal compensation operation for the multi-phase section and a single- VFDE and GDC - gate drive control for phase with independent control loops. Single- efficiency optimization phase (VTT) reference is always tracking multi- phases (VDDQ) scaled by a factor of 2. DPM - dynamic phase management Dual remote sense The L6759D supports power state transitions featuring VFDE, programmable DPM and GDC 0.5% output voltage accuracy maintaining the best efficiency over all loading Full-differential current sense across DCR conditions without compromising transient AVP - adaptive voltage positioning response. Dual independent adjustable oscillator The device assures fast and independent protection against load overcurrent, Dual current monitor under/overvoltage and feedback disconnections. Pre-biased output management The device is available in a VFQFPN48 6x6 mm Average and per-phase OC protection package. OV, UV and FB disconnection protection Dual VR RDY Table 1. Device summary VFQFPN48 6x6 mm package Order code Package Packing L6759D Tray Application VFQFPN48 6x6mm L6759DTR Tape and reel DDR3 memory supply for VR12 servers May 2012 Doc ID 023240 Rev 1 1/51 This is information on a product in full production. www.st.com 51Contents L6759D Contents 1 Typical application circuit and block diagram 5 1.1 Application circuit 5 1.2 Block diagram . 7 2 Pin description and connection diagrams . 8 2.1 Pin description 8 2.2 Thermal data 12 3 Electrical specifications . 13 3.1 Absolute maximum ratings 13 3.2 Electrical characteristics 13 4 Device configuration and pin-strapping tables 17 4.1 JMode . 17 4.2 Programming HiZ level . 18 5 Device description and operation . 20 5.1 Device initialization 20 6 Output voltage positioning . 22 6.1 Multi-phase section - phase programming 22 6.2 Multi-phase section - current reading and current sharing loop 22 6.3 Multi-phase section - defining load-line 23 6.4 Multi-phase section - IMON information 24 6.5 Single-phase section - disable . 25 6.6 Single-phase section - current reading . 25 6.7 Single-phase section - defining load-line . 25 6.8 Dynamic VID transition support 25 6.9 DVID optimization: REF 26 7 Output voltage monitoring and protection 28 7.1 Overvoltage . 28 7.2 Overcurrent . 28 2/51 Doc ID 023240 Rev 1