L9375TRLF STMicroelectronics

L9375TRLF Eight channel valve driver Datasheet - production data 16 bit serial peripheral interface (SPI), up to 5 MHz with diagnostics Battery compatible supply voltage Detailed load diagnostics Over load protection 0 03 Open load (off-state) PowerSO-36 Under current Under voltage Temperature warning and shutdown Power or signal GND loss Features Recirculation diode loss Eight protected low-side drivers with Silent valve driver test diagnostics Four 0.16 (typ) low side outputs (Q1 - Description Q4) The L9375TRLF is a SPI controlled octal channel Four 0.2 (typ) PWM controlled outputs low side driver with integrated recirculation (Q5 - Q8) diodes. All outputs with 35 V (min) zener clamp The output duty cycle (Q5 - Q8) can be Programmable output timer programmed individually. It is possible to program Clock monitor two consecutive output duty cycles per channel as well as an individual duration time for each Integrated recirculation diodes (Q5-Q8 only) channel actuation (all channels). Table 1. Device summary Order code Package Packing L9375TRLF PowerSO-36 (slug down) Tube March 2014 DocID026134 Rev 1 1/65 This is information on a product in full production. www.st.comContents L9375TRLF Contents 1 Block diagram 8 2 Pins description 9 3 Electrical specifications . 11 3.1 Absolute maximum ratings .11 3.2 ESD susceptibility . 12 3.2.1 HBM 12 3.2.2 MM . 12 3.3 Electrical characteristics 12 3.3.1 Supply current 12 3.3.2 Output power stages . 12 3.3.3 Recirculation diode 14 3.3.4 Output timing characteristics . 14 3.3.5 Output configuration Q1 - Q4 . 16 3.3.6 Output configuration Q5 - Q8 . 16 3.3.7 Logic inputs / outputs . 17 3.3.8 Logic outputs (MISO) . 17 3.3.9 Output stage diagnostic functions . 18 3.3.10 General diagnostic functions . 18 3.3.11 Filtering times 19 3.3.12 Internal oscillator 19 3.3.13 SPI timing characteristics SPICLK, MISO, MOSI, SPICS . 20 4 Circuit description 21 4.1 SPI serial peripheral interface . 21 4.1.1 General protocol 22 4.1.2 SPI failure detection 23 4.1.3 Data transfer . 23 4.1.4 Address decoder 24 4.1.5 Parity generator . 24 4.1.6 Initial MISO information . 24 4.1.7 Register map . 24 4.2 Clock 25 2/65 DocID026134 Rev 1