LD39300DT12-R STMicroelectronics

LD39300 Ultra low drop BICMOS voltage regulator Datasheet - production data Applications Microprocessor power supply DSPs power supply Post regulators for switching power supplies High efficiency linear regulator Description The LD39300 is a fast ultra low drop linear regulator which operates from 2.5 V to 6 V input supply. Features A wide range of output options are available. The 3 A guaranteed output current low drop voltage, low noise, and low quiescent Ultra low dropout voltage (200 mV typ. current make it suitable for low voltage 3 A load, 40 mV typ. 600 mA load) microprocessor and memory applications. The Very low quiescent current (1.2 mA typ. device is developed on a BiCMOS process which 3 A load, 1 A max 25 C in off mode) allows low quiescent current operation Logic-controlled electronic shutdown independently of output load current. Current and thermal internal limit 1.5 % output voltage tolerance 25 C Fixed and ADJ output voltages: 1.22 V, ADJ Temperature range: -40 to 125 C Fast dynamic response to line and load changes Stable with ceramic capacitor Available in PPAK and DPAK Table 1: Device summary Part number Output voltage DPAK PPAK LD39300DT12-R 1.22 V LD39300PT-R ADJ from 1.22 to 5.0 V March 2017 DocID13160 Rev 3 1/22 www.st.com This is information on a product in full production. Contents LD39300 Contents 1 Diagram ............................................................................................ 3 2 Pin configuration ............................................................................. 4 3 Typical application circuits ............................................................. 5 4 Maximum ratings ............................................................................. 7 5 Electrical characteristics ................................................................ 8 6 Typical performance characteristics ........................................... 10 7 Application notes .......................................................................... 13 7.1 External capacitors .......................................................................... 13 7.2 Input capacitor ................................................................................. 13 7.3 Output capacitor .............................................................................. 13 7.4 Thermal note ................................................................................... 13 7.5 Inhibit input operation ...................................................................... 13 8 Package information ..................................................................... 14 8.1 DPAK package information ............................................................. 14 8.2 PPAK package information ............................................................. 17 8.3 PPAK and DPAK packing information ............................................. 19 9 Revision history ............................................................................ 21 2/22 DocID13160 Rev 3