LNBP21 LNBP SUPPLY AND CONTROL IC WITH 2 STEP-UP CONVERTER AND I C INTERFACE COMPLETE INTERFACE BETWEEN LNB 2 TM AND I C BUS BUILT-IN DC/DC CONTROLLER FOR SINGLE 12V SUPPLY OPERATION ACCURATE BUILT-IN 22KHz TONE OSCILLATOR SUITS WIDELY ACCEPTED STANDARDS PowerSO-20 SO-20 FAST OSCILLATOR START-UP FACILITATES TM DiSEqC ENCODING BUILT-IN 22KHz TONE DETECTOR TM SUPPORTS BI-DIRECTIONAL DiSEqC DESCRIPTION LOOP-THROUGH FUNCTION FOR SLAVE Intended for analog and digital satellite STB OPERATION receivers/SatTV, sets/PC cards, the LNBP21 is a LNB SHORT CIRCUIT PROTECTION AND monolithic voltage regulator and interface IC, DIAGNOSTIC assembled in SO-20 and PowerSO-20, CABLE LENGTH DIGITAL COMPENSATION specifically designed to provide the power and the INTERNAL OVER TEMPERATURE 13/18V, 22KHz tone signalling to the LNB down PROTECTION converter in the antenna or to the multiswitch box. ESD RATING 4KV ON POWER In this application field, it offers a complete INPUT-OUTPUT PINS solution with extremely low component count, low Figure 1: Block Diagram LNBP21 Gate LT1 Sense Feedback Step-up Controller LT2 Vup OUT Vcc Preregul.+ U.V.lockout Enable +P.ON res. Linear Post-reg I Select Byp +Modulator +Protections V Select EXTM SDA Diagnostics SCL IC interf. DETIN Tone 22KHz ADDR Oscill. Detector DSQOUT DSQIN Rev. 3 October 2004 1/24LNBP21 power dissipation together with simple design and modulation is not used, the relevant pin can be left 2 TM I C standard interfacing. open. This IC has a built in DC/DC step-up controller The current limitation block has two thresholds that, from a single supply source ranging from 8 to that can be selected by the I bit of the SR the SEL 15V, generates the voltages that let the linear lower threshold is between 400 and 550mA post-regulator to work at a minimum dissipated (I =HIGH), while the higher threshold is SEL power. An UnderVoltage Lockout circuit will between 500 and 650mA (I =LOW). SEL disable the whole circuit when the supplied V CC The current protection block is SOA type. This drops below a fixed threshold (6.7V typically). The limits the short circuit current (I ) typically at SC internal 22KHz tone generator is factory trimmed 200mA with I =HIGH and at 300mA with SEL in accordance to the standards, and can be I =LOW when the output port is connected to 2 TM SEL controlled either by the I C interface or by a ground. dedicated pin (DSQIN) that allows immediate TM It is possible to set the Short Circuit Current DiSEqC data encoding (*). All the functions of protection either statically (simple current clamp) 2 TM this IC are controlled via I C bus by writing 6 or dynamically by the PCL bit of the SR when the bits on the System Register (SR, 8 bits). The PCL (Pulsed Current Limiting) bit is set to LOW, same register can be read back, and two bits will the overcurrent protection circuit works report the diagnostic status. When the IC is put in dynamically: as soon as an overload is detected, Stand-by (EN bit LOW), the power blocks are the output is shut-down for a time t , typically off disabled and the loop-through switch between 900ms. Simultaneously the OLF bit of the System LT1 and LT2 pins is closed, thus leaving all LNB Register is set to HIGH. After this time has powering and control functions to the Master elapsed, the output is resumed for a time t =1/ on Receiver (**). When the regulator blocks are 10t (typ.). At the end of t , if the overload is still off on active (EN bit HIGH), the output can be logic detected, the protection circuit will cycle again controlled to be 13 or 18 V (typ.) by mean of the through T and T . At the end of a full Ton in off on VSEL bit (Voltage SELect) for remote controlling which no overload is detected, normal operation is of non-DiSEqC LNBs. Additionally, it is possible to resumed and the OLF bit is reset to LOW. Typical increment by 1V (typ.) the selected voltage value T +T time is 990ms and it is determined by an on off to compensate for the excess voltage drop along internal timer. This dynamic operation can greatly the coaxial cable (LLC bit HIGH). In order to reduce the power dissipation in short circuit minimize the power dissipation, the output voltage condition, still ensuring excellent power-on start of the internal step-up converter is adjusted to up in most conditions (**). allow the linear regulator to work at minimum However, there could be some cases in which an dropout. Another bit of the SR is addressed to the highly capacitive load on the output may cause a remote control of non-DiSEqC LNBs: the TEN difficult start-up when the dynamic protection is (Tone ENable) bit. When it is set to HIGH, a chosen. This can be solved by initiating any power continuous 22KHz tone is generated regardless of start-up in static mode (PCL=HIGH) and then the DSQIN pin logic status. The TEN bit must be switching to the dynamic mode (PCL=LOW) after set LOW when the DSQIN pin is used for TM a chosen amount of time. When in static mode, DiSEqC encoding. The fully bidirectional TM the OLF bit goes HIGH when the current clamp DiSEqC interfacing is completed by the built-in limit is reached and returns LOW when the 22KHz tone detector. Its input pin (DETIN) must TM overload condition is cleared. be AC coupled to the DiSEqC bus, and the extracted PWK data are available on the This IC is also protected against overheating: DSQOUT pin (*). when the junction temperature exceeds 150C In order to improve design flexibility and to allow (typ.), the step-up converter and the linear implementation of newcoming LNB remote control regulator are shut off, the loop-trough switch is standards, an analogic modulation input pin is opened, and the OTF bit of the SR is set to HIGH. available (EXTM). An appropriate DC blocking Normal operation is resumed and the OTF bit is capacitor must be used to couple the modulating reset to LOW when the junction is cooled down to signal source to the EXTM pin. When external 140C (typ.). TM (*): External components are needed to comply to bi-directional DiSEqC bus hardware requirements. Full compliance of the whole appli- TM cation to DiSEqC specifications is not implied by the use of this IC. (**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must be externally limited. 2/24