M48T129Y M48T129V 5.0 or 3.3 V, 1 Mbit (128 Kbit x 8) TIMEKEEPER SRAM Not recommended for new design Features Integrated, ultra low power SRAM, real-time clock, power-fail control circuit, battery, and crystal BCD coded century, year, month, day, date, hours, minutes, and seconds 32 1 Battery low warning flag Automatic power-fail chip deselect and WRITE protection PMDIP32 module Two WRITE protect voltages: (V = power-fail deselect voltage) PFD M48T129Y: V = 4.5 to 5.5 V CC 4.2 V V 4.5 V PFD M48T129V: V = 3.0 to 3.6 V CC 2.7 V V 3.0 V PFD Conventional SRAM operation unlimited WRITE cycles Software controlled clock calibration for high accuracy applications 10 years of data retention and clock operation in the absence of power Self-contained battery and crystal in DIP package Microprocessor power-on reset (valid even during battery backup mode) Programmable alarm output active in battery backup mode RoHS compliant Lead-free second level interconnect June 2011 Doc ID 5710 Rev 5 1/28 This is information on a product still in production but not recommended for new designs. www.st.com 1Contents M48T129V, M48T129Y Contents 1 Description . 5 2 Operating modes 7 2.1 READ mode 8 2.2 WRITE mode 10 2.3 Data retention mode . 11 3 Clock operations . 12 3.1 TIMEKEEPER registers . 12 3.2 Reading the clock . 12 3.3 Setting the clock 12 3.4 Stopping and starting the oscillator . 12 3.5 Calibrating the clock . 14 3.6 Setting the alarm clock . 16 3.7 Watchdog timer 17 3.8 Power-on reset . 18 3.9 Battery low warning . 18 3.10 Initial power-on defaults 18 3.11 V noise and negative going transients . 19 CC 4 Maximum ratings . 20 5 DC and AC parameters 21 6 Package mechanical data 24 7 Environmental information . 25 8 Part numbering 26 9 Revision history . 27 2/28 Doc ID 5710 Rev 5