M74HC238 3 TO 8 LINE DECODER HIGH SPEED: t = 15ns (TYP.) at V = 6V PD CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 4mA (MIN) OH OL BALANCED PROPAGATION DELAYS: t t ORDER CODES PLH PHL WIDE OPERATING VOLTAGE RANGE: PACKAGE TUBE T & R V (OPR) = 2V to 6V CC DIP M74HC238B1R PIN AND FUNCTION COMPATIBLE WITH SOP M74HC238M1R M74HC238RM13TR 74 SERIES 238 TSSOP M74HC238TTR DESCRIPTION The M74HC238 is an high speed CMOS 3 TO 8 inhibited and all the 8 outputs go low. Three LINE DECODER fabricated with silicon gate enable inputs are provided to ease cascade 2 C MOS technology. connection and application of this address If the device is enabled, 3 binary select inputs (A, decoder in memory systems. B and C) determine which one of outputs will go All inputs are equipped with protection circuits high. When enable input G1 is heldLo or either against static discharge and transient excess G2A or G2B is heldHig decoding function is voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS July 2001 1/10M74HC238 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1, 2, 3 A, B, C Data Inputs 4, 5 G2A G2B Enable Input (Active LOW) 6 G1 Data Enable Input (Active HIGH) 15, 14, 13, Y0 to Y7 Outputs 12, 11, 10, 9, 7 8 GND Ground (0V) 16 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUTS SELECTED ENABLE SELECT OUTPUT G2B G2A G1 C B A Y0Y1 Y2 Y3 Y4Y5Y6 Y7 X X L X X X L LLL LL LL NONE X H X X X X L LLL LL LL NONE H X X X X X L LLL LL LL NONE LL H L L L H LLL LL LL Y0 LL H L L H L H LL LL LL Y1 LL H L H L L L H L LL LL Y2 LL H L H H L L L H LL LL Y3 LL H H L L L LLL H L LL Y4 LL H H L H L LLL L H LL Y5 LL H H H LL LLL LL H L Y6 LL H H H H L LLL LL L H Y7 X : Dont Care LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/10