M95128-DRMN8TP/K STMicroelectronics

M95128-DRE 128-Kbit serial SPI bus EEPROM - 105 C operation Datasheet - production data Features Compatible with the Serial Peripheral Interface (SPI) bus Memory array SO8 (MN) 128 Kbit (16 Kbytes) of EEPROM 150 mil width Page size: 64 bytes Write protection by block: 1/4, 1/2 or whole memory Additional Write lockable Page (Identification page) TSSOP8 (DW) Extended temperature and voltage range 169 mil width Up to 105 C (V from 1.7 V to 5.5 V) CC High speed clock frequency 20 MHz for V 4.5 V CC 10 MHz for V 2.5 V CC 5 MHz for V 1.7 V CC Schmitt trigger inputs for noise filtering WFDFPN8 (MF) DFN8 - 2 x 3 mm Short Write cycle time Byte Write within 4 ms Page Write within 4 ms Write cycle endurance 4 million Write cycles at 25 C 1.2 million Write cycles at 85 C 900 k Write cycles at 105 C Data retention more than 50 years at 105 C 200 years at 55 C ESD Protection (Human Body Model) 4000 V Packages RoHS-compliant and halogen-free (ECOPACK2 ) February 2017 DocID027469 Rev 2 1/42 This is information on a product in full production. www.st.comContents M95128-DRE Contents 1 Description . 6 2 Signal description . 8 2.1 Serial Data output (Q) 8 2.2 Serial Data input (D) 8 2.3 Serial Clock (C) . 8 2.4 Chip Select (S) 8 2.5 Hold (HOLD) 8 2.6 Write Protect (W) 8 2.7 V ground . 8 SS 2.8 V supply voltage . 9 CC 3 Operating features . 10 3.1 Active power and Standby power modes . 10 3.2 SPI modes 10 3.3 Hold mode .11 3.4 Protocol control and data protection 11 3.4.1 Protocol control . 11 3.4.2 Status Register and data protection 12 3.5 Identification page 13 4 Instructions . 15 4.1 Write Enable (WREN) . 16 4.2 Write Disable (WRDI) 16 4.3 Read Status Register (RDSR) . 17 4.4 Write Status Register (WRSR) . 18 4.5 Read from Memory Array (READ) 19 4.6 Write to Memory Array (WRITE) . 20 4.7 Read Identification Page (RDID) . 22 4.8 Write Identification Page (WRID) . 23 4.9 Read Lock Status (RDLS) 23 4.10 Lock Identification Page (LID) . 24 2/42 DocID027469 Rev 2