PM6670STR STMicroelectronics

PM6670S Complete DDR2/3 memory power supply controller Features Switching section (VDDQ) 4.5 V to 28 V input voltage range 0.9 V, 1 % voltage reference 1.8 V (DDR2) or 1.5 V (DDR3) fixed output voltages 0.9 V to 2.6 V adjustable output voltage VFQFPN-24 4x4 1.237 V 1 % reference voltage available Very fast load transient response using constant on-time control loop Description No R current sensing using low side SENSE The device PM6670S is a complete DDR2/3 MOSFETs R DS(ON) power supply regulator designed to meet JEDEC Negative current limit specifications. Latched OVP and UVP It integrates a constant on-time (COT) buck Soft-start internally fixed at 3 ms controller, a 2 Apk sink/source low drop out Selectable pulse skipping at light load regulator and a 15 mA low noise buffered Selectable no-audible (33 kHz) pulse skip reference. mode The COT architecture assures fast transient Ceramic output capacitors supported response supporting both electrolytic and ceramic Output voltage ripple compensation output capacitors. An embedded integrator VTT LDO and VTTREF control loop compensates the DC voltage error 2 Apk LDO with foldback for VTT due to the output ripple. Remote VTT sensing The 2 Apk sink/source linear regulator provides High-Z VTT output in S3 the memory termination voltage with fast load Ceramic output capacitors supported transient response. 15 mA low noise buffered reference The device is fully compliant with system sleep states S3 and S4/S5, providing LDO output high Applications impedance in suspend-to-RAM and tracking discharge of all outputs in suspend-to-disk. DDR2/3 memory supply Table 1. Device summary Notebook computers Order code Package Packaging Handheld and PDAs PM6670S Tube CPU and chipset I/O supplies VFQFPN-24 4x4 (Exposed pad) PM6670STR Tape and reel SSTL18, SSTL15 and HSTL bus termination February 2010 Doc ID 14432 Rev 4 1/54 www.st.com 54Contents PM6670S Contents 1 Typical application circuit 4 2 Pin settings 5 2.1 Connections 5 2.2 Pin description 6 3 Electrical data 8 3.1 Maximum rating . 8 3.2 Thermal data . 8 3.3 Recommended operating conditions . 9 4 Electrical characteristics 10 5 Typical operating characteristics . 14 6 Block diagram . 19 7 Device description . 20 7.1 VDDQ section - constant on-time PWM controller 21 7.1.1 Constant-on-time architecture 23 7.1.2 Output ripple compensation and loop stability 24 7.1.3 Pulse-skip and no-audible pulse-skip modes . 28 7.1.4 Mode-of-operation selection . 30 7.1.5 Current sensing and current limit 31 7.1.6 POR, UVLO and soft-start . 32 7.1.7 Power Good signal . 33 7.1.8 VDDQ output discharge . 34 7.1.9 Gate drivers 35 7.1.10 Reference voltage and bandgap 35 7.1.11 Over voltage and under voltage protections . 36 7.1.12 Device thermal protection . 36 7.2 VTTREF buffered reference and VTT LDO section . 37 7.2.1 VTT and VTTREF Soft-Start . 37 7.2.2 VTTREF and VTT outputs discharge . 37 2/54 Doc ID 14432 Rev 4