SPEAR310-2 STMicroelectronics

SPEAr310 Embedded MPU with ARM926 core, flexible memory support, extended set of powerful connectivity features Features ARM926EJ-S 333 MHz core High-performance 8-channel DMA Dynamic power-saving features Configurable peripheral functions multiplexed on 102 shared I/Os Memory: LFBGA289 (15 x 15 x 1.7 mm) 32 KB ROM and 8 KB internal SRAM LPDDR-333/DDR2-666 external memory interface JPEG CODEC accelerator Serial Flash Memory interface (SMI) Six 16-bit general purpose timers with programmable prescaler, 4 capture inputs Flexible static memory controller (FSMC) up to 16-bit data bus width, supporting Up to 102 GPIOs with interrupt capability NAND Flash External memory interface (EMI) up to 32- Applications bit data bus width, supporting NOR Flash and FPGAs The SPEAr310 embedded MPU is configurable for a range of telecom and networking Connectivity applications such as: 2 x USB 2.0 Host Routers, switches and gateways USB 2.0 Device Remote apparatus control 1 x fast Ethernet MII port 4 x fast Ethernet SMII ports Metering concentrators 1 x SSP Synchronous serial peripheral Table 1. Device summary (SPI, Microwire or TI protocol) with 4 chip selects Temp Order code Package Packing 2 1 x I C range, C 1 x fast IrDA interface LFBGA289 6 x UART interface SPEAR310-2 -40 to 85 (15x15 mm, Tray pitch 0.8 mm) 1x TDM/E1 HDLC interface with 128/32 timeslots per frame respectively 2x RS485 HDLC ports Security C3 Cryptographic accelerator Miscellaneous functions Integrated real time clock, watchdog, and system controller 8-channel 10-bit ADC, 1 Msps March 2010 Doc ID 16482 Rev 2 1/72 www.st.com 1Contents SPEAr310 Contents 1 Description . 8 2 Architecture overview . 11 2.1 CPU ARM 926EJ-S . 11 2.2 System controller . 12 2.2.1 Clock and reset system . 12 2.2.2 Power saving system mode control 13 2.2.3 Vectored interrupt controller (VIC) . 14 2.2.4 General purpose timers . 14 2.2.5 Watchdog timer . 14 2.2.6 RTC oscillator 14 2.3 Multichannel DMA controller 15 2.4 Embedded memory units . 15 2.5 Mobile DDR/DDR2 memory controller . 15 2.6 Serial memory interface 15 2.7 External memory interface (EMI) . 16 2.8 Flexible static memory controller (FSMC) 16 2.9 UARTs . 17 2.9.1 UART with hardware flow control 17 2.9.2 UARTs with software flow control . 17 2.10 Synchronous serial port (SSP) . 18 2.11 I2C 18 2.12 TDM/E1 HDLC controller . 19 2.12.1 TDM interface 19 2.12.2 E1 interface 19 2.13 RS485 HDLC ports . 19 2.13.1 HDLC controller . 20 2.14 GPIOs . 20 2.15 8-channel ADC . 21 2.16 SMII Ethernet controller 21 2.17 MII Ethernet controller . 22 2.18 USB2 host controller 23 2/72 Doc ID 16482 Rev 2