ST2100 STMicroelectronics

ST2100 Broadband powerline communication SoC optimized for audio/video streaming and consumer applications Datasheet - production data Master/slave SSI Two independent UARTs Fast IrDA Real-time clock Configurable serial port (SPORT) interface for external DSP and audio codec (ADC and DAC) 2 in I S mode Transport stream interface (video TS) Vectored interrupt controller (VIC) TFBGA 12 x 12 x 1.2 mm JTAG (IEEE1149.1) interface Three CPU instruction sets Features Applications Configurable HW engine for multiple HomePlug PHY and real-time MAC layers The STreamPlug ST2100 is configurable for a (a) processing supporting: wide range of consumer and industrial powerline applications such as: HomePlug AV and 1.0 standards HomePlug Green PHY standard Smart gateway Integrated analog front-end Powerline communication bridging, including wireless ARM926EJ-S 32-bit RISC CPU up to 333 MHz Smart grid (a) 8/16 bit DDR mobile at 166 MHz and DDR2 at Electric vehicle charging station 333 MHz memory controller In house audio/video distribution Serial memory interface Video surveillance 8/16-bits NOR Flash/NAND Flash and SRAM Home automation memories controllers Network Area Storage (NAS) Multichannel DMA controller Display panels control Ethernet 10/100 MAC with MII interface USB 2.0 Table 1. Device summary PCI Express and S-ATA Order Operating Package Packing code temp. range Color LCD (CLCD) controller JPEG codec accelerator TFBGA 12 x 12 x Tray, tape ST2100 -40 to +85 C 1.2 mm, Cryptographic coprocessor and reel pitch 0.5 mm Up to 40 GPIOs 2 Enhanced I S (digital audio interface) 2 a. Not intended for automotive usage . I C master/slave mode February 2018 DocID025777 Rev 2 1/38 This is information on a product in full production. www.st.comContents ST2100 Contents 1 Description . 6 2 Main features . 7 3 Architecture description 9 3.1 CPU subsystem 10 3.2 System bus 10 3.3 Memory subsystem 11 3.4 Expi subsystem .11 3.5 Basic subsystem 11 3.6 High-speed connectivity subsystem . 12 3.7 Low-speed connectivity subsystem . 12 3.8 Application subsystem . 13 3.9 Clock and reset system 13 4 Pin descriptions . 14 4.1 Dedicated pins . 14 4.2 Shared I/O pins (MFIOs) . 22 4.3 Required external components 27 5 Memory map 28 6 Clocking parameters 30 6.1 Master clock (MCLK) 30 6.2 Real-time clock (RTC) . 31 6.3 PCIe/SATA clock . 31 7 Electrical characteristics 32 7.1 Absolute maximum ratings 32 7.2 Power consumption . 32 7.3 DC electrical characteristics . 33 7.4 Power-up and reset sequence . 34 7.5 Internal 2.5 V linear regulator 34 2/38 DocID025777 Rev 2