STM32MP157C/F Arm dual Cortex -A7 800 MHz + Cortex -M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog, crypto Datasheet - production data Features TFBGA LFBGA Includes ST state-of-the-art patented LFBGA448 (18 18mm) TFBGA361 (12 12 mm) technology LFBGA354 (16 16mm) TFBGA257 (10 10 mm) min Pitch 0.5mm Pitch 0.8mm Core Internal temperature sensors 32-bit dual-core Arm Cortex -A7 Low-power modes: Sleep, Stop and Standby L1 32-Kbyte I / 32-Kbyte D for each core DDR memory retention in Standby mode 256-Kbyte unified level 2 cache Controls for PMIC companion chip Arm NEON and Arm TrustZone 32-bit Arm Cortex -M4 with FPU/MPU Low-power consumption Up to 209 MHz (Up to 703 CoreMark ) Total current consumption down to 2 A (Standby mode, no RTC, no LSE, no Memories BKPSRAM, no RETRAM) External DDR memory up to 1 Gbyte up to LPDDR2/LPDDR3-1066 16/32-bit Clock management up to DDR3/DDR3L-1066 16/32-bit Internal oscillators: 64 MHz HSI oscillator, 708 Kbytes of internal SRAM: 256 Kbytes of 4 MHz CSI oscillator, 32 kHz LSI oscillator AXI SYSRAM + 384 Kbytes of AHB SRAM + External oscillators: 8-48 MHz HSE oscillator, 64 Kbytes of AHB SRAM in Backup domain 32.768 kHz LSE oscillator and 4 Kbytes of SRAM in Backup domain 6 PLLs with fractional mode Dual mode Quad-SPI memory interface Flexible external memory controller with up to General-purpose input/outputs 16-bit data bus: parallel interface to connect Up to 176 I/O ports with interrupt capability external ICs and SLC NAND memories with up Up to 8 secure I/Os to 8-bit ECC Up to 6 Wakeup, 3 tampers, 1 active tamper Security/safety Secure boot, TrustZone peripherals, active Interconnect matrix tamper 2 bus matrices Cortex -M4 resources isolation 64-bit Arm AMBA AXI interconnect, up to 266 MHz Reset and power management 32-bit Arm AMBA AHB interconnect, up 1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os) to 209 MHz POR, PDR, PVD and BOR 3 DMA controllers to unload the CPU On-chip LDOs (RETRAM, BKPSRAM, DSI 1.2 V, USB 1.8 V, 1.1 V) 48 physical channels in total Backup regulator (~0.9 V) May 2021 DS12505 Rev 6 1/262 This is information on a product in full production. www.st.comSTM32MP157C/F 1 high-speed general-purpose master direct up to WXGA (1366 768) 60 fps or up to memory access controller (MDMA) Full HD (1920 1080) 30 fps Pixel clock up to 90 MHz 2 dual-port DMAs with FIFO and request router capabilities for optimal peripheral Two layers with programmable colour LUT management MIPI DSI 2 data lanes up to 1 Gbps each Up to 37 communication peripherals Up to 29 timers and 3 watchdogs 2 6 I C FM+ (1 Mbit/s, SMBus/PMBus) 2 32-bit timers with up to 4 IC/OC/PWM or 4 UART + 4 USART (12.5 Mbit/s, ISO7816 pulse counter and quadrature (incremental) interface, LIN, IrDA, SPI slave) encoder input 6 SPI (50 Mbit/s, including 3 with full duplex 2 16-bit advanced motor control timers 2 I S audio class accuracy via internal audio PLL 10 16-bit general-purpose timers (including 2 or external clock) basic timers without PWM) 2 4 SAI (stereo audio: I S, PDM, SPDIF Tx) 5 16-bit low-power timers SPDIF Rx with 4 inputs RTC with sub-second accuracy and hardware HDMI-CEC interface calendar MDIO Slave interface 2 4 Cortex -A7 system timers (secure, non- secure, virtual, hypervisor) 3 SDMMC up to 8-bit (SD / eMMC / SDIO) 1 SysTick M4 timer 2 CAN controllers supporting CAN FD protocol, out of which one supports time- 3 watchdogs (2 independent and window) triggered CAN (TTCAN) Hardware acceleration 2 USB 2.0 high-speed Host + 1 USB 2.0 full-speed OTG simultaneously AES 128, 192, 256, TDES or 1 USB 2.0 high-speed Host HASH (MD5, SHA-1, SHA224, SHA256), + 1 USB 2.0 high-speed OTG HMAC simultaneously 2 true random number generator 10/100M or Gigabit Ethernet GMAC (3 oscillators each) IEEE 1588v2 hardware, 2 CRC calculation unit MII/RMII/GMII/RGMII 8- to 14-bit camera interface up to 140 Mbyte/s Debug mode Arm CoreSight trace and debug: SWD and 6 analog peripherals JTAG interfaces 2 ADCs with 16-bit max. resolution (12 bits 8-Kbyte embedded trace buffer up to 4.5 Msps, 14 bits up to 4 Msps, 16 bits up to 3.6 Msps) 3072-bit fuses including 96-bit unique ID, 1 temperature sensor up to 1184-bit available for user 2 12-bit D/A converters (1 MHz) All packages are ECOPACK2 compliant 1 digital filters for sigma delta modulator (DFSDM) with 8 channels/6 filters Internal or external ADC/DAC reference V REF+ Graphics 3D GPU: Vivante - OpenGL ES 2.0 Up to 26 Mtriangle/s, 133 Mpixel/s LCD-TFT controller, up to 24-bit // RGB888 2/262 DS12505 Rev 6