STMPE1801 Xpander Logic 18-bit enhanced port expander with keypad controller Features 18 GPIOs configurable as GPI, GPO, keypad matrix, special key or dedicated key function Operating voltage: 1.65 - 3.6 V Hardware keypad controller (KPC) (10 x 8 matrix with 4 optional dedicated keys maximum) Keypad controller capable of detecting keypress in hibernation mode Flip-chip CSP 25 (2.03 x 2.03 mm) Interrupt output (open drain) pin Advanced power management system Ultra-low standby mode current Programmable pull-up resistors for all GPIO Description pins ESD performance on GPIO pins: The STMPE1801 is a GPIO (general purpose 8 kV human body model input/output) port expander capable of interfacing (JESD22 A114-C) a main digital ASIC via the two-line bidirectional 2 bus (I C). A separate GPIO expander IC is often ESD performance on V , GND, INT , R , CC B STB SCL, SDA pins: used in mobile multimedia platforms to resolve 3 kV human body model the problem of the limited number of GPIOs (JESD22 A114-C) typically available on digital engines. The STMPE1801 offers high flexibility, as each I/O can be configured as input, output, special key, keypad matrix or dedicated key function. This device is designed to include very low quiescent current, and a wakeup feature for each I/O, to optimize the power consumption of the device. Potential applications for the STMPE1801 include portable media players, game consoles, mobile and smart phones. Table 1. Device summary Order code Package Packaging Flip-chip CSP 25 (2.03 x 2.03 mm) STMPE1801BJR Tape and reel 0.4 mm pitch March 2011 Doc ID 17884 Rev 3 1/60 www.st.com 60Contents STMPE1801 Contents 1 Block diagram 4 2 Pin settings 5 2.1 Pin connection 5 2.2 Pin description 5 2.3 GPIO pin functions . 6 3 Maximum ratings 8 3.1 Absolute maximum ratings . 8 3.2 Thermal data . 8 4 Electrical specification . 9 4.1 DC electrical characteristics 9 4.2 Input/Output DC electrical characteristics 10 5 Register address . 11 6 I2C specification . 14 6.1 I2C related pins 14 6.2 I2C addressing . 14 6.3 Start condition . 14 6.4 Stop condition . 14 6.5 Acknowledge bit (ACK) . 15 6.6 Data input . 15 6.7 Memory addressing . 15 6.8 Operation modes . 15 6.9 General call address 17 7 System controller 18 7.1 System level registers . 18 7.2 States of operation 20 7.2.1 Auto-hibernate 20 7.2.2 Keypress detect in the Hibernate mode 21 2/60 Doc ID 17884 Rev 3