STSMIA832 1.8 V / 2.8 V high speed dual differential line receivers, standard mobile imaging architecture (SMIA) decoder deserializer Features Sub-low voltage differential signaling inputs: V = 100 mV min. with R = 100 , C = 10 pF ID T L High signaling rate: f = 650 Mbps max (D+,D-,STRB+,STRB-) IN f = 82 MHz max (CLK) OUT f = 82 Mbps max (for each data line D1-D8) OUT TFBGA25 Very high speed strobe to clock: t ~ t = 5.2 ns (typ) at V = 2.8 V PLH PHL DD V = 1.8 V L Operating voltage range: V (OPR) = 2.65 V to 3.6 V DD Description V (OPR) = 1.65 V to 1.95 V L Symmetrical output impedance The STSMIA832 receiver converts the subLVDS (D1-D8, H-SYNC, V-SYNC, CLK): clock/datastream (up to 650 Mbps throughput II I = I = 4 mA (min) at V = 2.65 V bandwidth) back into parallel 8 bits of OH OL DD V = 1.8 V CMOS/LVTTL. The device recognizes the SMIA L 32 bit start of frame (SOF), end of frame (EOF), Low power dissipation (disabled: EN = gnd): start of line (SOL) and end of line (EOL) I = I + I = 10 A (Max) SOFF DD L sequences to generate the H-SYNC and V-SYNC SMIA specification compliant signals. Output LVTTL clock (up to 82 MHz) is Support for SMIA CCP RAW8, RAW10 and transmitted in parallel with data. Output data are RAW12 8-bit packet rising-edge strobes. This chipset is an ideal means to link mobile camera modules to CLASS 0 and CLASS 1, 2 supported (config. Baseband processors. In order to minimize static by CLASS SEL) current consumption, it is possible to shut down CMOS logic input threshold the device when the interface is not being used by (EN, SYNC SEL, CLASS SEL): a power-down (EN) pin that reduces the V = 0.3 x V V = 1.65 V to 1.95 V IL L L maximum current consumption to 10 A making V = 0.7 x V V = 1.65 V to 1.95 V IH L L this device ideal for portable applications like 3.6 V tolerant on inputs mobile phone and portable battery equipment. A (EN, SYNC SEL, CLASS SEL) configurable input (Class Sel) is provided to select different CLASS (0 or 1, 2) mode inside the 32 BIT synchronization codes (SOF, EOF, SMIA standard specifications. SOL, EOL) The STSMIA832 is offered in a TFBGA package Leadfree TFBGA package to optimize PCB space. All inputs and outputs are (RoHS restriction of hazardous substances) equipped with protection circuits against static discharge, giving them ESD immunity from Applications transient excess voltage. The STSMIA832 is characterized for operation over the commercial Feature phone (Mid-end 2 - 8 MPixel) temperature range - 40 C to 85 C. PDA, digital camera Notebook, eBook (webcam), UMPC, MID May 2010 Doc ID 12174 Rev 5 1/25 www.st.com 25 Contents STSMIA832 Contents 1 Schematic diagram 3 2 Pin configuration 4 2.1 Pin descriptions for reference: 5 2.2 Supplementary notes: SMIA specification . 6 3 Application information 9 3.1 Inputs . 9 3.2 Power down mode . 9 3.3 Power saving at the inputs 10 3.4 Switching off digital blocks 10 3.5 Disabling the outputs 10 3.6 Load capacitance . 10 3.7 Board layout . 11 3.8 Decoupling capacitors . 11 4 Maximum ratings . 13 5 Electrical characteristics 14 6 Frame structure 17 7 Timing diagram 18 8 Package mechanical data 20 9 Order code 23 10 Revision history . 24 2/25 Doc ID 12174 Rev 5