DESCRIPTION www.epc-co.com Demonstration Board Contact us: The development board is in a half bridge topology with onboard driver, supply and bypass capacitors. The board contains all critical gate drives, featuring the EPC8000 family of high frequency en- components and layout for optimal switching performance. There www.epc-co.com EPC9022/23/24/25/27/28/29/30 hancement mode (eGaN) field effect transistors (FETs). The pur - are also various probe points to facilitate simple waveform mea- Renee Yawger Bhasy Nair pose of these development boards is to simplify the evaluation surement and efficiency calculation. A complete block diagram of WW Marketing Global FAE Support Quick Start Guide process of the EPC8000 family of eGaN FETs by including all the the circuit is given in Figure 1. Office: +1.908.475.5702 Office: +1.972.805.8585 critical components on a single board that can be easily connected Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 For more information on the EPC8000 family of eGaN FETs, please renee.yawger epc-co.com bhasy.nair epc-co.com into any existing converter. Half Bridge with Gate Drive for EPC8000 Family refer to the datasheets available from EPC at www.epc-co.com. The Stephen Tsang Peter Cheng The development board is 2 x 1.5 and contains two eGaN FETs in a datasheet should be read in conjunction with this quick start guide. Sales, Asia FAE Support, Asia half bridge configuration using the Texas Instruments LM5113 gate Mobile: +852.9408.8351 Mobile: +886.938.009.706 Table 1: Performance Summary (TA = 25C) stephen.tsang epc-co.com peter.cheng epc-co.com SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 7 12 V DD When using 40 V devices EPC8004, EPC8007, EPC8008 28* V VIN Bus Input Voltage Range When using 65 V devices EPC8002, EPC8005, EPC8009 45* V When using 100 V devices EPC8003, EPC8010 70* V When using 40 V devices EPC8004, EPC8007, EPC8008 40 V VOUT Switch Node Output Voltage When using 65 V devices EPC8002, EPC8005, EPC8009 65 V When using 100 V devices EPC8003, EPC8010 100 V When using 40 V device EPC8004 4.4 A When using 40 V device EPC8007 3.5* A When using 40 V device EPC8008 2.2* A EPC Products are distributed exclusively through Digi-Key. I Switch Node Output Current When using 65 V device EPC8002 1.6* A OUT www.digikey.com When using 65 V device EPC8005 2.2* A When using 65 V device EPC8009 3.5* A When using 100 V device EPC8003 2.2* A Demonstration Board Notification The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not When using 100 V device EPC8010 3.2* A designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As V PWM Logic Input Voltage Threshold Input High 3.5 6 V board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not PWM RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Input Low 0 1.5 V Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. Minimum High State Input Pulse Width VPWM rise and fall time < 10ns 20 ns Minimum Low State Input Pulse Width V rise and fall time < 10ns 50 ns PWM EPC reserves the right at any time, without notice, to change said circuitry and specifications. * Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to refresh high side bootstrap supply voltage. Quick Start Procedure 7 V 12 V Gate Drive Supply V Supply Gate Drive DD V Half-Bridge with Bypass DD The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement + Regulator V IN Gate Drive Supply setup and follow the procedure below: (Note Polarity) A LM5113 Logic and 1. With power off, connect the input power supply bus to +V (J5, J6) and ground / return to VIN (J7, J8). IN PWM See Table 1 I IN Gate OUT Dead-time for max + Input + 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. Driver Adjust Switch Node V V VIN Supply IN 3. With power off, connect the gate drive input to +V (J1, Pin-1) and ground return to V (J1, Pin-2). DD DD (For E ciency External Circuit 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. Measurement) 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on V as indicated in the table below: OUT PWM Input Figure 1: Block Diagram of Development Board a. EPC9022, 65 V d. EPC9025, 65 V g. EPC9029, 65 V EPC EFFICIENT POWER CONVERSION b. EPC9023, 100 V e. EPC9027, 40 V h. EPC9030, 100 V c. EPC9024, 40 V f. EPC9028, 40 V Figure 2: Proper Connection and Measurement Setup 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. Do not use probe ground lead 9. For shutdown, please follow steps in reverse. Do not let NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope touch the probe technique. low-side die THERMAL CONSIDERATIONS Minimize loop Place probe The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon tip on pad devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rat - Figure 4: Typical Waveforms for V = 28 V to 3.3 V/4 A (5 MHz) Buck converter IN ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. CH2: (V ) Switch node voltage CH4: V Input voltage OUT PWM Figure 3: Proper Measurement of Switch Node OUT NOTE. The development board does not have any current or thermal protection on board.DESCRIPTION www.epc-co.com Demonstration Board Contact us: The development board is in a half bridge topology with onboard driver, supply and bypass capacitors. The board contains all critical gate drives, featuring the EPC8000 family of high frequency en- components and layout for optimal switching performance. There www.epc-co.com EPC9022/23/24/25/27/28/29/30 hancement mode (eGaN) field effect transistors (FETs). The pur - are also various probe points to facilitate simple waveform mea- Renee Yawger Bhasy Nair pose of these development boards is to simplify the evaluation surement and efficiency calculation. A complete block diagram of WW Marketing Global FAE Support Quick Start Guide process of the EPC8000 family of eGaN FETs by including all the the circuit is given in Figure 1. Office: +1.908.475.5702 Office: +1.972.805.8585 critical components on a single board that can be easily connected Mobile: +1.908.619.9678 Mobile: +1.469.879.2424 For more information on the EPC8000 family of eGaN FETs, please renee.yawger epc-co.com bhasy.nair epc-co.com into any existing converter. Half Bridge with Gate Drive for EPC8000 Family refer to the datasheets available from EPC at www.epc-co.com. The Stephen Tsang Peter Cheng The development board is 2 x 1.5 and contains two eGaN FETs in a datasheet should be read in conjunction with this quick start guide. Sales, Asia FAE Support, Asia half bridge configuration using the Texas Instruments LM5113 gate Mobile: +852.9408.8351 Mobile: +886.938.009.706 Table 1: Performance Summary (TA = 25C) stephen.tsang epc-co.com peter.cheng epc-co.com SYMBOL PARAMETER CONDITIONS MIN MAX UNITS V Gate Drive Input Supply Range 7 12 V DD 40 V devices EPC9024, EPC9027, EPC9028 28* V V Bus Input Voltage Range 65 V devices EPC9022, EPC9025, EPC9029 45* V IN 100 V devices EPC9023, EPC9030 70* V 40 V devices EPC9024, EPC9027, EPC9028 40 V V Switch Node Output Voltage 65 V device EPC9022, EPC9025, EPC9029 65 V OUT 100 V devices EPC9023, EPC9030 100 V 40 V device EPC9024 4.4* A 40 V device EPC9027 3.5* A 40 V device EPC9028 2.2* A EPC Products are distributed exclusively through Digi-Key. IOUT Switch Node Output Current 65 V device EPC9022 1.6* A www.digikey.com 65 V device EPC9025 2.2* A 65 V device EPC9029 3.5* A 100 V device EPC9023 2.2* A Demonstration Board Notification 100 V device EPC9030 3.2* A The EPC boards are intended for product evaluation purposes only and is not intended for commercial use. As an evaluation tool, it is not V PWM Logic Input Voltage Threshold Input High 3.5 6 V designed for compliance with the European Union directive on electromagnetic compatibility or any other such directives or regulations. As PWM board builds are at times subject to product availability, it is possible that boards may contain components or assembly materials that are not Input Low 0 1.5 V RoHS compliant. Efficient Power Conversion Corporation (EPC) makes no guarantee that the purchased board is 100% RoHS compliant. No Licenses are implied or granted under any patent right or other intellectual property whatsoever. EPC assumes no liability for applications F Minimum Switching Frequency Bootstrap Capacitor Limited 500 kHz MIN assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind. Minimum High State Input Pulse Width V rise and fall time < 10ns 20 ns PWM EPC reserves the right at any time, without notice, to change said circuitry and specifications. Minimum Low State Input Pulse Width VPWM rise and fall time < 10ns 50 ns * Assumes inductive load, maximum current depends on die temperature actual maximum current with be subject to switching frequency, bus voltage and thermals. Limited by time needed to refresh high side bootstrap supply voltage. Quick Start Procedure 7 V 12 V Gate Drive Supply Gate Drive V Supply DD V Half-Bridge with Bypass DD The development board is easy to set up to evaluate the performance of the eGaN FET. Refer to Figure 2 for proper connect and measurement Regulator + V IN Gate Drive Supply setup and follow the procedure below: (Note Polarity) A LM5113 Logic and 1. With power off, connect the input power supply bus to +V (J5, J6) and ground / return to VIN (J7, J8). IN PWM Gate OUT I Dead-time IN Input <28 V + 2. With power off, connect the switch node of the half bridge OUT (J3, J4) to your circuit as required. + Driver Adjust Switch Node V V VIN Supply IN 3. With power off, connect the gate drive input to +V (J1, Pin-1) and ground return to V (J1, Pin-2). DD DD (For E ciency 4. With power off, connect the input PWM control signal to PWM (J2, Pin-1) and ground return to any of the remaining J2 pins. External Circuit Measurement) 5. Turn on the gate drive supply make sure the supply is between 7 V and 12 V range. 6. Turn on the bus voltage to the required value (do not exceed the absolute maximum voltage on V as indicated in the table below: OUT PWM Input Figure 1: Block Diagram of Development Board a. EPC9022, 65 V d. EPC9025, 65 V g. EPC9029, 65 V b. EPC9023, 100 V e. EPC9027, 40 V h. EPC9030, 100 V EPC EFFICIENT POWER CONVERSION c. EPC9024, 40 V f. EPC9028, 40 V Figure 2: Proper Connection and Measurement Setup 7. Turn on the controller / PWM input source and probe switching node to see switching operation. 8. Once operational, adjust the bus voltage and load PWM control within the operating range and observe the output switching behavior, efficiency and other parameters. Do not use probe ground lead 9. For shutdown, please follow steps in reverse. Do not let NOTE. When measuring the high frequency content switch node (OUT), care must be taken to avoid long ground leads. Measure the switch node (OUT) by placing the oscilloscope probe tip probe tip through the large via on the switch node (designed for this purpose) and grounding the probe directly across the GND terminals provided. See Figure 3 for proper scope touch the probe technique. low-side die THERMAL CONSIDERATIONS Minimize loop Place probe The development board showcases the EPC8000 family of eGaN FET. Although the electrical performance surpasses that for traditional silicon tip on pad devices, their relatively smaller size does magnify the thermal management requirements. The development board is intended for bench evaluation with low ambient temperature and convection cooling. The addition of heat-sinking and forced air cooling can significantly increase the current rat - Figure 4: Typical Waveforms for V = 28 V to 3.3 V/4 A (5 MHz) Buck converter IN ing of these devices, but care must be taken to not exceed the absolute maximum die temperature of 125C. CH2: (V ) Switch node voltage CH4: V Input voltage OUT PWM Figure 3: Proper Measurement of Switch Node OUT NOTE. The development board does not have any current or thermal protection on board.