Integrated Synthesizer and VCO Data Sheet ADF4360-7 FEATURES GENERAL DESCRIPTION Output frequency range: 350 MHz to 1800 MHz The ADF4360-7 is an integrated integer-N synthesizer and Divide-by-2 output voltage controlled oscillator (VCO). The ADF4360-7 center 3.0 V to 3.6 V power supply frequency is set by external inductors. This allows a frequency 1.8 V logic compatibility range of between 350 MHz to 1800 MHz. In addition, a divide- Integer-N synthesizer by-2 option is available, whereby the user receives an RF output Programmable dual-modulus prescaler 8/9, 16/17 of between 175 MHz and 900 MHz. Programmable output power level Control of all the on-chip registers is through a simple 3-wire 3-wire serial interface interface. The device operates with a power supply ranging from Analog and digital lock detect 3.0 V to 3.6 V and can be powered down when not in use. Hardware and software power-down mode APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AV DV R CE DD DD SET ADF4360-7 MUXOUT MULTIPLEXER 14-BIT R REF IN COUNTER LOCK MUTE DETECT CLK 24-BIT 24-BIT DATA FUNCTION DATA REGISTER CHARGE LATCH CP LE PUMP PHASE V VCO COMPARATOR V TUNE L1 L2 C C C N INTEGER REGISTER RF A OUT VCO OUTPUT CORE STAGE 13-BIT B RF B COUNTER OUT LOAD PRESCALER P/P+1 LOAD 5-BIT A COUNTER N = (BP + A) DIVSEL = 1 2 DIVSEL = 2 AGND DGND CPGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no re- sponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20042013 Analog Devices, Inc. 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Technical Support www.analog.com MULTIPLEXER 04441-001ADF4360-7 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 MUXOUT and Lock Detect ...................................................... 11 Applications ....................................................................................... 1 Input Shift Register .................................................................... 11 General Description ......................................................................... 1 VCO ............................................................................................. 11 Functional Block Diagram .............................................................. 1 Output Stage ................................................................................ 12 Revision History ............................................................................... 2 Latch Structure ........................................................................... 13 Specifications ..................................................................................... 3 Power-Up ..................................................................................... 17 Timing Characteristics ..................................................................... 5 Control Latch .............................................................................. 19 Absolute Maximum Ratings ............................................................ 6 N Counter Latch ......................................................................... 20 Transistor Count ........................................................................... 6 R Counter Latch ......................................................................... 20 ESD Caution .................................................................................. 6 Applications ..................................................................................... 21 Pin Configuration and Function Descriptions ............................. 7 Frequency Generator ................................................................. 21 Typical Performance Characteristics ............................................. 8 Choosing the Correct Inductance Value ................................. 22 Circuit Description ......................................................................... 10 Fixed Frequency LO ................................................................... 22 Reference Input Section ............................................................. 10 Interfacing ................................................................................... 23 Prescaler (P/P + 1) ...................................................................... 10 PCB Design Guidelines for Chip Scale Package........................... 23 A and B Counters ....................................................................... 10 Output Matching ........................................................................ 24 R Counter .................................................................................... 10 Outline Dimensions ....................................................................... 25 PFD and Charge Pump .............................................................. 10 Ordering Guide .......................................................................... 25 REVISION HISTORY 3/13Rev. C to Rev. D 11/04Rev. 0 to Rev. A. Changes to Prescaler (P/P + 1) Section ....................................... 10 Updated Format .................................................................. Universal Changes to General Description ..................................................... 1 11/12Rev. B to Rev. C Changes to Specifications ................................................................. 3 Changes to Table 3 ............................................................................ 6 Changes to the Reference Input Section...................................... 10 Updated Outline Dimensions ....................................................... 25 Changes to Power-Up Section ...................................................... 17 Added Table 10 ............................................................................... 17 2/12Rev. A to Rev. B Added Figure 22 ............................................................................. 17 Changes to Figure 3 and Table 4 ..................................................... 8 Updated Outline Dimensions ....................................................... 25 Changes to Output Matching Section .......................................... 24 Updated Outline Dimensions ....................................................... 25 2/04Revision 0: Initial Version. Changes to Ordering Guide .......................................................... 25 Rev. D Page 2 of 28