DESIGN KIT AVAILABLE
DS3141/DS3142/DS3143/DS3144
Single/Dual/Triple/Quad
DS3/E3 Framers
www.maxim-ic.com
GENERAL DESCRIPTION FEATURES
The DS3141, DS3142, DS3143, and DS3144
One/Two/Three/Four Independent DS3/E3
(DS314x) devices include all necessary circuitry to
Framers on a Single Die
frame and format up to four separate DS3 or E3
Framing and Formatting to M23 DS3, C-Bit Parity
channels. Each framer in these devices is
DS3, and G.751 E3
independently configurable to support M23 DS3,
LIU Interface can be Binary (NRZ) or Dual-Rail
C-Bit Parity DS3, or G.751 E3. The framers interface
(POS/NEG)
to a variety of line interface units (LIUs),
B3ZS/HDB3 Encoder and Decoder
microprocessor buses, and other system
Generate and Detect DS3/E3 Alarms
components without glue logic. Each DS3/E3 framer
Integrated HDLC Controller for Each Channel
has its own HDLC controller, FEAC controller, and
Integrated FEAC Controller for Each Channel
BERT, as well as full support for error detection and
generation, performance monitoring, and loopbacks. Integrated Bit Error-Rate Tester (BERT) for Each
Channel
Large Performance-Monitoring Counters
APPLICATIONS
Line, Diagnostic, and Payload Loopbacks
SONET/SDH Muxes
Externally Controlled Transmit Overhead
PDH Muxes
Insertion Port
Digital Cross-Connect Systems
Support External Timing or Loop-Timing
Access Concentrators
ATM and Frame Relay Equipment
Framers can be Powered Down When Not Used
Routers
8-Bit Processor Port Supports Muxed or
Nonmuxed Bus Operation (Intel or Motorola)
FUNCTIONAL DIAGRAM 3.3V Supply with 5V Tolerant I/O
144-Pin, 13mm x 13mm CSBGA Package
IEEE 1149.1 JTAG Support
LIU
SYSTEM
EACH FRAMER
INTERFACE
INTERFACE
ORDERING INFORMATION
CLK
POS/NRZ
TRANSMIT DATA
NEG
NO. OF
SYNC
FORMATTER
CLK
PART TEMP RANGE PIN-PACKAGE
FRAMERS
OVERHEAD
DS3141 1 0C to +70C 144 CSBGA
POS/NRZ
CLK
DS3141N 1 144 CSBGA
-40C to +85C
RECEIVE
NEG/LCV
DATA
DS3142 2 144 CSBGA
0C to +70C
CLK FRAMER
SYNC
DS3142 2 -40C to +85C 144 CSBGA
Dallas DS3143 3 0C to +70C 144 CSBGA
Semiconductor
DS3143N 3 144 CSBGA
-40C to +85C
DS314x
DS3144 4 0C to +70C 144 CSBGA
DS3144N 4 -40C to +85C 144 CSBGA
Pin Configurations appear at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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TABLE OF CONTENTS
1. BLOCK DIAGRAM.......................................................................................................................... 6
2. APPLICATION EXAMPLE .............................................................................................................. 6
3. MAIN FEATURES ........................................................................................................................... 7
4. STANDARDS COMPLIANCE ......................................................................................................... 8
5. PIN DESCRIPTION ......................................................................................................................... 9
5.1 TRANSMIT FORMATTER LIU INTERFACE PINS................................................................................. 9
5.2 RECEIVE FRAMER LIU INTERFACE PINS......................................................................................... 9
5.3 TRANSMIT FORMATTER SYSTEM INTERFACE PINS ........................................................................ 10
5.4 RECEIVE FRAMER SYSTEM INTERFACE PINS ................................................................................ 12
5.5 CPU BUS INTERFACE PINS......................................................................................................... 14
5.6 JTAG INTERFACE PINS............................................................................................................... 14
5.7 SUPPLY, TEST, AND RESET PINS................................................................................................. 14
6. REGISTERS.................................................................................................................................. 15
6.1 STATUS REGISTER DESCRIPTION ................................................................................................ 17
7. FUNCTIONAL DESCRIPTION ...................................................................................................... 18
7.1 PIN INVERSIONS AND FORCE HIGH/LOW ...................................................................................... 18
7.2 TRANSMITTER LOGIC .................................................................................................................. 18
7.2.1 Transmit Clock ..................................................................................................................................... 18
7.2.2 Loss-of-Clock Detection....................................................................................................................... 19
7.3 RECEIVER LOGIC........................................................................................................................ 19
7.4 ERROR INSERTION...................................................................................................................... 20
7.5 LOOPBACKS............................................................................................................................... 20
7.5.1 Line Loopback...................................................................................................................................... 20
7.5.2 Diagnostic Loopback............................................................................................................................ 20
7.5.3 Payload Loopback................................................................................................................................ 20
7.5.4 BERT and Loopback Interaction .......................................................................................................... 20
7.6 COMMON AND LINE INTERFACE REGISTERS ................................................................................. 22
7.6.1 Master Status Register (MSR) ............................................................................................................. 28
7.7 DS3/E3 FRAMER ....................................................................................................................... 32
7.7.1 DS3/E3 Framer Register Description................................................................................................... 32
7.8 DS3/E3 PERFORMANCE ERROR COUNTERS................................................................................ 42
7.9 BERT........................................................................................................................................ 45
7.9.1 BERT Register Description .................................................................................................................. 45
7.10 HDLC CONTROLLER ............................................................................................................... 53
7.10.1 Receive Operation ............................................................................................................................... 53
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