STM32MP151A
Arm Cortex -A7 650 MHz + Cortex -M4 MPU,
TFT, 35 comm. interfaces, 25 timers, adv. analog
Datasheet - production data
Features
TFBGA
LFBGA
Core
LFBGA448 (18 18mm) TFBGA361 (12 12 mm)
32-bit Arm Cortex -A7
LFBGA354 (16 16mm) TFBGA257 (10 10 mm)
min Pitch 0.5mm
Pitch 0.8mm
L1 32-Kbyte I / 32-Kbyte D
256-Kbyte unified level 2 cache
Controls for PMIC companion chip
Arm NEON and Arm TrustZone
Low-power consumption
32-bit Arm Cortex -M4 with FPU/MPU
Total current consumption down to 6 A
Up to 209 MHz (Up to 703 CoreMark )
Clock management
Memories
Internal oscillators: 64 MHz HSI oscillator,
External DDR memory up to 1 Gbyte
4 MHz CSI oscillator, 32 kHz LSI oscillator
up to LPDDR2/LPDDR3-1066 16/32-bit
External oscillators: 8-48 MHz HSE oscillator,
up to DDR3/DDR3L-1066 16/32-bit
32.768 kHz LSE oscillator
708 Kbytes of internal SRAM: 256 KB of AXI
5 PLLs with fractional mode
SYSRAM + 384 KB of AHB SRAM + 64 KB of
AHB SRAM in backup domain and 4 KB of
General-purpose input/outputs
SRAM in backup domain
Up to 176 I/O ports with interrupt capability
Dual mode Quad-SPI memory interface
Up to 8 secure I/Os
Flexible external memory controller with up to
Up to 6 Wakeup, 3 Tamper, 1 Active-
16-bit data bus: parallel interface to connect
Tamper
external ICs and SLC NAND memories with up
to 8-bit ECC
Interconnect matrix
Security/safety
2 bus matrices
TrustZone peripherals, active tamper
64-bit Arm AMBA AXI interconnect, up to
266 MHz
Cortex -M4 resources isolation
32-bit Arm AMBA AHB interconnect, up
to 209 MHz
Reset and power management
1.71 V to 3.6 V I/Os supply (5 V-tolerant I/Os)
3 DMA controllers to unload the CPU
POR, PDR, PVD and BOR
48 physical channels in total
On-chip LDOs (RETRAM, BKPSRAM, USB
1 high-speed general-purpose master direct
1.8 V, 1.1 V)
memory access controller (MDMA)
Backup regulator (~0.9 V)
2 dual-port DMAs with FIFO and request
Internal temperature sensors
router capabilities for optimal peripheral
management
Low-power modes: Sleep, Stop and Standby
LPDDR2/3 retention in Standby mode
February 2019 DS12500 Rev 1 1/245
This is information on a product in full production. www.st.comSTM32MP151A
Up to 35 communication peripherals RTC with sub-second accuracy and hardware
calendar
2
6 I C FM+ (1 Mbit/s, SMBus/PMBus)
4 Cortex -A7 system timers (secure, non-
4 UART + 4 USART (12.5 Mbit/s, ISO7816
secure, virtual, hypervisor)
interface, LIN, IrDA, SPI slave)
1 SysTick M4 timer
6 SPI (50 Mbit/s, including 3 with full duplex
2
3 watchdogs (2 independent and window)
I S audio class accuracy via internal audio PLL
or external clock)
Hardware acceleration
2
4 SAI (stereo audio: I S, PDM, SPDIF Tx)
HASH (MD5, SHA-1, SHA224, SHA256),
SPDIF Rx with 4 inputs
HMAC
HDMI-CEC interface
2 true random number generator
MDIO Slave interface
(3 oscillators each)
3 SDMMC up to 8-bit (SD / eMMC / SDIO)
2 CRC calculation unit
2 USB 2.0 high-speed Host
Debug mode
+ 1 USB 2.0 full-speed OTG simultaneously
or 1 USB 2.0 high-speed Host
Arm CoreSight trace and debug: SWD and
+ 1 USB 2.0 high-speed OTG
JTAG interfaces
simultaneously
8-Kbyte embedded trace buffer
10/100M or Gigabit Ethernet GMAC
3072-bit fuses including 96-bit unique ID,
IEEE 1588v2 hardware,
MII/RMII/GMII/RGMII up to 1184-bit available for user
8- to 14-bit camera interface up to 140 Mbyte/s
All packages are ECOPACK 2 compliant
6 analog peripherals
2 ADCs with 16-bit max. resolution (12 bits
5 Msps, 14 bits 4.4 Msps, 16 bits 250 ksps)
1 temperature sensor
2 12-bit D/A converters (1 MHz)
1 digital filters for sigma delta modulator
(DFSDM) with 8 channels/6 filters
Internal or external ADC/DAC reference V
REF+
Graphics
LCD-TFT controller, up to 24-bit // RGB888
up to WXGA (1366 768) @60 fps
Two layers with programmable colour LUT
Up to 25 timers and 3 watchdogs
2 32-bit timers with up to 4 IC/OC/PWM or
pulse counter and quadrature (incremental)
encoder input
2 16-bit advanced motor control timers
10 16-bit general-purpose timers (including 2
basic timers without PWM)
5 16-bit low-power timers
2/245 DS12500 Rev 1