74HC237D(BJ) Toshiba

74HC237D CMOS Digital Integrated Circuits Silicon Monolithic 74HC237D74HC237D74HC237D74HC237D 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description 3-to-8 Line Decoder/Latch 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2. The 3-bit binary data is stored into the input latch on the high level of GL. The value of this data determines which one of the outputs will go low. When the enable input G1 is held low or G2 is held high, decoding function is inhibited and all the 8 outputs go high. The two enable inputs are provided to ease cascade connection and permits the application address decoder for memory system. All inputs are equipped with protection circuits against static discharge or transient excess voltage. 3. 3. FeaturesFeatures 3. 3. FeaturesFeatures (1) High speed: t = 12 ns (typ.) at V = 5 V pd CC (2) Low power dissipation: I = 4.0 A (max) at T = 25 CC a (3) Balanced propagation delays: t t PLH PHL (4) Wide operating voltage range: V = 2.0 V to 6.0 V CC(opr) 4. 4. 4. 4. PackagingPackagingPackagingPackaging SOIC16 Start of commercial production 2016-05 2016 Toshiba Corporation 2016-08-04 1 Rev.3.074HC237D 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 7. 7. 7. 7. IEC Logic SymbolIEC Logic SymbolIEC Logic SymbolIEC Logic Symbol 2016 Toshiba Corporation 2016-08-04 2 Rev.3.0