74VHC123AFT,74VHC221AFT CMOS Digital Integrated Circuits Silicon Monolithic 74VHC123AFT,74VHC221AFT74VHC123AFT,74VHC221AFT74VHC123AFT,74VHC221AFT74VHC123AFT,74VHC221AFT 1. 1. Functional DescriptionFunctional Description 1. 1. Functional DescriptionFunctional Description Dual Monostable Multivibrator 74VHC123AFT: Retriggerable 74VHC221AFT: Non-Retriggerable 2. 2. 2. 2. GeneralGeneralGeneralGeneral The 74VHC123A/221AFT are high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology. There are two trigger inputs, A input (negative edge), and B input (positive edge). These inputs are valid for a slow rise/fall time signal (t = t = 1 s) as they are schmitt trigger inputs. This device may also be triggered by r f using CLR input (positive edge). After triggering, the output stays in a MONOSTABLE state for a time period determined by the external resistor and capacitor (R , C ). A low level at the CLR input breaks this state. X X Limits for C and R are: X X External capacitor, C : No limit X External resistor, R : V = 2.0 V more than 5 k X CC V 3.0 V more than 1 k CC An input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 V to 3 V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages. 3. 3. Features (Note)Features (Note) 3. 3. Features (Note)Features (Note) (1) AEC-Q100 (Rev. H) (Note 1) (2) Wide operating temperature range: T = -40 to 125 opr (3) High speed: Propagation delay time = 8.1 ns (typ.) at V = 5 V CC (4) Low power dissipation: Standby state: 4.0 A (max) at T = 25 a Active state: 750 A (max) at T = 25 a (5) High noise immunity: V = V = 28 % V (min) NIH NIL CC (6) Power-down protection is provided on all inputs. (7) Balanced propagation delays: t t PLH PHL (8) Wide operating voltage range: V = 2.0 V to 5.5 V CC(opr) (9) Pin and function compatible with 74HC123,74HC221 type. Note: In the case of using only one circuit,CLR should be tied to GND, R /C C QQ should be tied to OPEN, X X X the other inputs should be tied to V or GND. CC Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales representative. Start of commercial production 2013-05 2016 Toshiba Corporation 2017-03-08 1 Rev.7.074VHC123AFT,74VHC221AFT 4. 4. 4. 4. PackagingPackagingPackagingPackaging TSSOP16B 5. 5. 5. 5. Pin AssignmentPin AssignmentPin AssignmentPin Assignment 6. 6. 6. 6. MarkingMarkingMarkingMarking 74VHC123AFT 74VHC221AFT 2016 Toshiba Corporation 2017-03-08 2 Rev.7.0